公开(公告)号：US11495674B2

公开(公告)日：2022-11-08

申请号：US16725802

申请日：2019-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Chan ,  Derek Chen ,  Liang-Yin Chen ,  Chien-I Kuo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L21/02 ,  H01L21/225 ,  H01L21/324

Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.

公开(公告)号：US11018259B2

公开(公告)日：2021-05-25

申请号：US15161139

申请日：2016-05-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang Lo ,  Tung-Wen Cheng ,  Chia-Ling Chan ,  Mu-Tsang Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/223

Abstract: A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall of the gate structure. At least a bottom portion of the gate spacer has a plurality of dopants therein.

公开(公告)号：US10727226B2

公开(公告)日：2020-07-28

申请号：US15652719

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chia-Ling Chan ,  Liang-Yin Chen ,  Huicheng Chang

IPC: H01L29/165 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L21/84

Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a gate structure and a source/drain feature. The gate structure is positioned over a fin structure. The source/drain feature is positioned adjacent to the gate structure. A portion of the source/drain feature embedded in the fin structure has an upper sidewall portion adjacent to a top surface of the fin structure and a lower sidewall portion below the upper sidewall portion. A first curve radius of the upper sidewall portion is different from a second curve radius of the lower sidewall portion in a cross-sectional view substantially along the longitudinal direction of the fin structure.

公开(公告)号：US20190355816A1

公开(公告)日：2019-11-21

申请号：US16531421

申请日：2019-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-I Kuo ,  Shao-Fu Fu ,  Chia-Ling Chan ,  Yi-Fang Pai ,  Li-Li Su ,  Wei Hao Lu ,  Wei Te Chiang ,  Chii-Horng Li

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/22 ,  H01L21/02 ,  H01L29/36 ,  H01L29/167 ,  H01L29/78 ,  H01L21/223

Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.

公开(公告)号：US10374038B2

公开(公告)日：2019-08-06

申请号：US15922643

申请日：2018-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-I Kuo ,  Chii-Horng Li ,  Chia-Ling Chan ,  Li-Li Su ,  Yi-Fang Pai ,  Wei Te Chiang ,  Shao-Fu Fu ,  Wei Hao Lu

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/167 ,  H01L29/36 ,  H01L21/223 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/306

Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.

公开(公告)号：US10134902B2

公开(公告)日：2018-11-20

申请号：US15460006

申请日：2017-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Chia-Chun Lan ,  Chia-Ling Chan ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/70 ,  H01L29/78 ,  H01L29/161 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L21/311 ,  H01L27/092

Abstract: A system is configured to perform plasma related fabrication processes. The system includes a process chamber and a wafer stage positioned within the process chamber. The wafer stage is configured to secure a process wafer. The system further includes a bottom electrode positioned beneath the wafer stage, a top electrode positioned external to the chamber, and a plasma distribution mechanism. The plasma distribution mechanism is reconfigurable to allow for more than one plasma distribution profile.

公开(公告)号：US11610885B2

公开(公告)日：2023-03-21

申请号：US16924541

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chia-Ling Chan ,  Liang-Yin Chen ,  Huicheng Chang

IPC: H01L21/265 ,  H01L21/22 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84

Abstract: A method for forming a semiconductor structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes depositing a dopant source layer over the gate structure. The method also includes driving dopants of the dopant source layer into the fin structure. The method also includes removing the dopant source layer. The method also includes annealing the dopants in the fin structure to form a doped region. The method also includes etching the doped region and the fin structure below the doped region to form a recess. The method also includes growing a source/drain feature in the recess.

公开(公告)号：US11264505B2

公开(公告)日：2022-03-01

申请号：US17027078

申请日：2020-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Chan ,  Yen-Chun Lin

IPC: H01L29/78 ,  H01L21/22 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L23/532 ,  H01L29/423 ,  H01L21/768 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/324

Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, forming a first spacer over the dummy gate structure, implanting a first dopant in the fin to form a doped region of the fin adjacent the first spacer, removing the doped region of the fin to form a first recess, wherein the first recess is self-aligned to the doped region, and epitaxially growing a source/drain region in the first recess.

公开(公告)号：US10714619B2

公开(公告)日：2020-07-14

申请号：US16046740

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Chia-Chun Lan ,  Chia-Ling Chan ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/311 ,  H01L29/78 ,  H01L29/161 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: A method for fabricating a semiconductor device includes forming a doped semiconductor layer on a substrate and forming a fin structure disposed on the doped semiconductor layer. The fin structure is doped with a p-type dopant. The method further includes forming a source/drain region within an upper portion of the fin structure and forming a fin sidewall along a lower portion of the fin structure. The fin sidewall has the p-type dopant.

公开(公告)号：US20190267471A1

公开(公告)日：2019-08-29

申请号：US15907427

申请日：2018-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Chan ,  Derek Chen ,  Liang-Yin Chen ,  Chien-I Kuo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L21/02 ,  H01L21/225 ,  H01L21/324

Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.