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    On-chip oscilloscope
    11.
    发明授权
    On-chip oscilloscope 有权

    公开(公告)号：US11567105B2

    公开(公告)日：2023-01-31

    申请号：US17326147

    申请日：2021-05-20

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chung-Peng Hsieh ,  Chih-Chiang Chang ,  Chung-Chieh Yang

    IPC: G01R19/00 ,  G01R13/00 ,  G01R13/02 ,  G01R31/28 ,  G01R31/317

    Abstract: A device includes a control circuit, a scope circuit, and a time-to-current converter. The control circuit is configured to receive a voltage signal from a voltage-controlled oscillator, delay the voltage signal for a delay time to generate a first control signal, and to generate a second control signal according to the first control signal and the voltage signal. The scope circuit is configured to generate a first current signal in response to the second control signal and the voltage signal. The time-to-current converter is configured generate a second current signal according to the first control signal, the voltage signal, a first switch signal, and a test control signal.

    Source/Drain Formation with Reduced Selective Loss Defects
    13.
    发明申请
    Source/Drain Formation with Reduced Selective Loss Defects 有权

    公开(公告)号：US20220328660A1

    公开(公告)日：2022-10-13

    申请号：US17809963

    申请日：2022-06-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chiang Chang ,  Ming-Hua Yu ,  Li-Li Su

    IPC: H01L29/66 ,  H01L21/20 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78

    Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

    Method of fabricating a semiconductor device structure
    14.
    发明授权
    Method of fabricating a semiconductor device structure 有权

    公开(公告)号：US10269648B1

    公开(公告)日：2019-04-23

    申请号：US15857381

    申请日：2017-12-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kun-Mu Li ,  Chih-Chiang Chang ,  Wen-Chu Hsiao

    IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

    Abstract: Methods of fabricating a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes epitaxially growing a source/drain structure covering the fin structure. In addition, the method includes epitaxially growing a capping layer over the source/drain structure. The capping layer has a top portion and a lower portion under the top portion. The top portion has a first thickness and the lower portion has a second. A ratio of the first thickness to the second thickness is in a range of about 1.01 to about 2. The method also includes etching the top portion and the lower portion of the capping layer. The method further includes forming a silicide layer over the source/drain structure and a contact over the silicide layer.

    ELECTRO-MIGRATION BARRIER FOR CU INTERCONNECT
    16.
    发明申请
    ELECTRO-MIGRATION BARRIER FOR CU INTERCONNECT 审中-公开
    用于CU互连的电动移动障碍

    公开(公告)号：US20170053875A1

    公开(公告)日：2017-02-23

    申请号：US15343393

    申请日：2016-11-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Su-Jen Sung ,  Chih-Chiang Chang ,  Chia-Ho Chen

    IPC: H01L23/532

    CPC classification number: H01L23/53238 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure relates to an integrated circuit device and an associated method of formation. The integrated circuit device includes a substrate, and a conductive metal interconnect line arranged within a dielectric material disposed over the substrate. An interfacial layer is in contact with an upper surface of the conductive metal interconnect line. An upper dielectric layer is arranged over the interfacial layer. A middle dielectric layer is arranged between the upper dielectric layer and the interfacial layer.

    Abstract translation: 本公开涉及集成电路器件和相关联的形成方法。 集成电路器件包括衬底和布置在设置在衬底上的电介质材料内的导电金属互连线。 界面层与导电金属互连线的上表面接触。 上介电层布置在界面层上。 中介电层布置在上电介质层和界面层之间。

    Electro-migration barrier for Cu interconnect
    17.
    发明授权
    Electro-migration barrier for Cu interconnect 有权
    Cu互连的电迁移屏障

    公开(公告)号：US09490209B2

    公开(公告)日：2016-11-08

    申请号：US13967596

    申请日：2013-08-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Su-Jen Sung ,  Chih-Chiang Chang ,  Chia-Ho Chen

    IPC: H01L23/532 ,  H01L21/768

    CPC classification number: H01L23/53238 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuit devices and method of forming them. The devices include a dielectric barrier layer formed over a copper-containing metal interconnect structure. The dielectric barrier layer inhibits electro-migration of Cu. The dielectric barrier layer includes a metal-containing layer that forms an interface with the interconnect structure. Incorporating metal within the interfacial layer improves adhesion of the dielectric barrier layer to copper lines and the like and provides superior electro-migration resistance over the operating lifetime of the devices.

    Abstract translation: 集成电路器件及其形成方法。 这些器件包括在含铜金属互连结构之上形成的介电阻挡层。 介电阻挡层抑制Cu的电迁移。 电介质阻挡层包括与互连结构形成界面的含金属层。 将界面层内的金属掺入提高介电阻挡层对铜线等的粘附性，并且在器件的使用寿命内提供优异的耐电迁移性。

    Digitally controlled delay line circuit and method
    19.
    发明授权
    Digitally controlled delay line circuit and method 有权

    公开(公告)号：US11082035B1

    公开(公告)日：2021-08-03

    申请号：US17030160

    申请日：2020-09-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chung-Peng Hsieh ,  Chih-Chiang Chang ,  Yung-Chow Peng

    IPC: H03K5/14 ,  H03K5/24 ,  H03K5/134 ,  H03K5/131

    Abstract: A digitally controlled delay line (DCDL) includes an input terminal, an output terminal, and a plurality of stages configured to propagate a signal along a first signal path from the input terminal to a selectable return stage of the plurality of stages, and along a second signal path from the return stage of the plurality of stages to the output terminal. Each stage of the plurality of stages includes first and second inverters configured to selectively propagate the signal along the first signal path, third and fourth inverters configured to selectively propagate the signal along the second signal path, and a fifth inverter configured to selectively propagate the signal from the first signal path to the second signal path.

    Electro-migration barrier for Cu interconnect
    20.
    发明授权
    Electro-migration barrier for Cu interconnect 有权

    公开(公告)号：US10163795B2

    公开(公告)日：2018-12-25

    申请号：US15343393

    申请日：2016-11-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Su-Jen Sung ,  Chih-Chiang Chang ,  Chia-Ho Chen

    IPC: H01L23/532 ,  H01L21/768

    Abstract: The present disclosure relates to an integrated circuit device and an associated method of formation. The integrated circuit device includes a substrate, and a conductive metal interconnect line arranged within a dielectric material disposed over the substrate. An interfacial layer is in contact with an upper surface of the conductive metal interconnect line. An upper dielectric layer is arranged over the interfacial layer. A middle dielectric layer is arranged between the upper dielectric layer and the interfacial layer.

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