公开(公告)号：US11699733B2

公开(公告)日：2023-07-11

申请号：US17397099

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first gate-all-around (GAA) transistor over a first region of a substrate and a second GAA transistor over a second region of the substrate. The first GAA transistor includes a plurality of first channel members stacked along a first direction vertical to a top surface of the substrate and a first gate structure over the plurality of first channel members. The second GAA transistor includes a plurality of second channel members stacked along a second direction parallel to the top surface of the substrate and a second gate structure over the plurality of second channel members. The plurality of first channel members and the plurality of second channel members comprise a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane. The first direction is normal to the first crystal plane and the second direction is normal to the second crystal plane.

公开(公告)号：US11664451B2

公开(公告)日：2023-05-30

申请号：US17216241

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chieh Yang ,  Li-Yang Chuang ,  Pei-Yu Wang ,  Wei Ju Lee ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/0847

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

公开(公告)号：US20230113266A1

公开(公告)日：2023-04-13

申请号：US18053236

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L21/308 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66

Abstract: A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.

公开(公告)号：US11581436B2

公开(公告)日：2023-02-14

申请号：US17113821

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Hsing Hsu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Sai-Hooi Yeong

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.

公开(公告)号：US11532720B2

公开(公告)日：2022-12-20

申请号：US16996094

申请日：2020-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Hou-Yu Chen ,  Ching-Wei Tsai

IPC: H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor layer, a gate structure, a source/drain epitaxial structure, a backside dielectric cap, and an inner spacer. The gate structure wraps around the semiconductor layer. The source/drain epitaxial structure is adjacent the gate structure and electrically connected to the semiconductor layer. The backside dielectric cap is disposed under and in direct contact with the gate structure. The inner spacer is in direct contact with the gate structure and the backside dielectric cap.

公开(公告)号：US11532715B2

公开(公告)日：2022-12-20

申请号：US17397596

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wei Tsai ,  Yi-Bo Liao ,  Cheng-Ting Chung ,  Yu-Xuan Huang ,  Kuan-Lun Cheng

IPC: H01L29/417 ,  H01L29/45 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed on opposite sides of a plurality of conductive layers. A dielectric layer overlies the first source/drain region, the second source/drain region, and the plurality of conductive layers. An electrical contact extends through the dielectric layer and the first source/drain region, where a first surface of the electrical contact is a surface of the electrical contact that is closest to the substrate, a first surface of the plurality of conductive layers is a surface of the plurality of conductive layers that is closest to the substrate, and the first surface of the electrical contact is closer to the substrate than the first surface of the plurality of conductive layers.

公开(公告)号：US20220336461A1

公开(公告)日：2022-10-20

申请号：US17859638

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

Abstract: A semiconductor device according to the present disclosure includes a first plurality of gate-all-around (GAA) devices in a first device area and a second plurality of GAA devices in a second device area. Each of the first plurality of GAA devices includes a first vertical stack of channel members extending along a first direction, and a first gate structure over and around the first vertical stack of channel members. Each of the second plurality of GAA devices includes a second vertical stack of channel members extending along a second direction, and a second gate structure over and around the second vertical stack of channel members. Each of the first plurality of GAA devices includes a first channel length and each of the second plurality of GAA devices includes a second channel length smaller than the first channel length.

公开(公告)号：US11362191B2

公开(公告)日：2022-06-14

申请号：US16415136

申请日：2019-05-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Yi Chuang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/51 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66

Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-κ gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.

公开(公告)号：US20220165885A1

公开(公告)日：2022-05-26

申请号：US17671156

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Yu-Xuan Huang ,  Pei-Yu Wang ,  Cheng-Ting Chung ,  Ching-Wei Tsai ,  Hou-Yu Chen

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

公开(公告)号：US20220029028A1

公开(公告)日：2022-01-27

申请号：US17498093

申请日：2021-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a fin substrate having a first dopant concentration; an anti-punch through (APT) layer disposed over the fin substrate, wherein the APT layer has a second dopant concentration that is greater than the first dopant concentration; a nanostructure including semiconductor layers disposed over the APT layer; a gate structure disposed over the nanostructure and wrapping each of the semiconductor layers, wherein the gate structure includes a gate dielectric and a gate electrode; a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature disposed over the APT layer, wherein the gate structure is disposed between the first epitaxial S/D feature and the second epitaxial S/D feature; and an isolation layer disposed between the APT layer and the fin substrate, wherein a material of the isolation layer is the same as a material of the gate dielectric.