公开(公告)号：US11545397B2

公开(公告)日：2023-01-03

申请号：US17143698

申请日：2021-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Jhih-Rong Huang ,  Yen-Tien Tung ,  Tzer-Min Shen ,  Fu-Ting Yen ,  Gary Chan ,  Keng-Chu Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/8234 ,  H01L21/3065

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

公开(公告)号：US11152491B2

公开(公告)日：2021-10-19

申请号：US16299531

申请日：2019-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Han-Yu Lin ,  Chansyun David Yang ,  Fang-Wei Lee ,  Tze-Chung Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L29/78 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L29/06

Abstract: A method for forming a semiconductor device structure is provided. The method for forming a semiconductor device structure includes forming a fin structure over a substrate. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method for forming the semiconductor device structure also includes removing the first semiconductor layers of the fin structure in a channel region thereby exposing the second semiconductor layers of the fin structure. The method for forming the semiconductor device structure also includes forming a dielectric material surrounding the second semiconductor layers, and treating a first portion of the dielectric material. The method for forming the semiconductor device structure also includes etching the first portion of the dielectric material to form gaps, and filling the gaps with a gate stack.

公开(公告)号：US11107904B2

公开(公告)日：2021-08-31

申请号：US16592281

申请日：2019-10-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Chansyun David Yang ,  Tze-Chung Lin ,  Fang-Wei Lee ,  Fo-Ju Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L29/06

Abstract: A method of fabricating a semiconductor device includes forming a structure including multiple nanowires vertically stacked above a substrate; depositing a dielectric material layer wrapping around the nanowires; performing a treatment process to a surface portion of the dielectric material layer; selectively etching the surface portion of the dielectric material layer; repeating the steps of performing the treatment process and selectively etching until the nanowires are partially exposed; and forming a gate structure engaging the nanowires.

公开(公告)号：US20210202247A1

公开(公告)日：2021-07-01

申请号：US17201744

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei Jhan ,  Han-Yu Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/40 ,  H01L21/3105 ,  H01L21/265

Abstract: A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, where the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.

公开(公告)号：US12224210B2

公开(公告)日：2025-02-11

申请号：US18313783

申请日：2023-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Yi-Ruei Jhan ,  Fang-Wei Lee ,  Tze-Chung Lin ,  Chao-Hsien Huang ,  Li-Te Lin ,  Pinyen Lin ,  Akira Mineji

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/764 ,  H01L27/088

Abstract: A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.

公开(公告)号：US12136570B2

公开(公告)日：2024-11-05

申请号：US17550670

申请日：2021-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith Khaderbad ,  Wei-Yen Woon ,  Cheng-Ming Lin ,  Han-Yu Lin ,  Szu-Hua Chen ,  Jhih-Rong Huang ,  Tzer-Min Shen

IPC: H01L21/8234 ,  H01L21/48 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

公开(公告)号：US12021125B2

公开(公告)日：2024-06-25

申请号：US17377861

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tze-Chung Lin ,  Pinyen Lin ,  Fang-Wei Lee ,  Li-Te Lin ,  Han-Yu Lin

IPC: H01L29/417 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41775 ,  H01L21/3065 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/78696

Abstract: The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.

公开(公告)号：US20230020731A1

公开(公告)日：2023-01-19

申请号：US17533372

申请日：2021-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Szu-Hua Chen ,  Kuan-Kan Hu ,  Kenichi Sano ,  Po-Cheng Wang ,  Wei-Yen Woon ,  Pinyen Lin ,  Che Chi Shih

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.

公开(公告)号：US20220130693A1

公开(公告)日：2022-04-28

申请号：US17572162

申请日：2022-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Yi-Ruei Jhan ,  Fang-Wei Lee ,  Li-Te Lin ,  Pinyen Lin ,  Tze-Chung Lin

IPC: H01L21/67 ,  H01L21/677 ,  C23C16/452

Abstract: The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber for etching; a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer; a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer; and a heating mechanism embedded in the process chamber and is operable to perform a baking process to remove a by-product generated during the etching. The heating mechanism is integrated between the reflective mirror and a gas distribution plate of the processing chamber.

公开(公告)号：US11222794B2

公开(公告)日：2022-01-11

申请号：US16044314

申请日：2018-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Yi-Ruei Jhan ,  Fang-Wei Lee ,  Li-Te Lin ,  Pinyen Lin ,  Tze-Chung Lin

IPC: H01L21/67 ,  H01L21/677 ,  C23C16/452

Abstract: The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber for etching; a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer; a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer; and a heating mechanism embedded in the process chamber and is operable to perform a baking process to remove a by-product generated during the etching. The heating mechanism is integrated between the reflective mirror and a gas distribution plate of the processing chamber.