公开(公告)号：US11810611B2

公开(公告)日：2023-11-07

申请号：US17716446

申请日：2022-04-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hiroki Noguchi ,  Yih Wang

IPC: G11C11/406 ,  G11C11/4091 ,  G11C11/4076

CPC classification number: G11C11/40611 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/40626

Abstract: A memory system is provided. The memory system includes a controller configured to refresh a memory array at a first temperature before a first refresh time that is acquired from a lookup table and corresponds to a time period for stored data in the memory array being lost at the first temperature. After the controller acquires a second refresh time from the lookup table, the controller resets a refresh time period to refresh the memory array before the second refresh time. The second refresh time corresponds to a time period for stored data in the memory array being lost at a second temperature different from the first temperature. The refresh time period corresponds to a time period after refreshing the memory array.

公开(公告)号：US20230345738A1

公开(公告)日：2023-10-26

申请号：US18335816

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shy-Jay Lin ,  Chien-Min Lee ,  Hiroki Noguchi ,  MingYuan Song ,  Yen-Lin Huang ,  William Joseph Gallagher

IPC: H10B61/00 ,  H01L23/528 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H10B61/22 ,  H01L23/528 ,  H01L21/76898 ,  H01L21/823475

Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.

公开(公告)号：US11502241B2

公开(公告)日：2022-11-15

申请号：US16731864

申请日：2019-12-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： MingYuan Song ,  Shy-Jay Lin ,  William J. Gallagher ,  Hiroki Noguchi

IPC: H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  H01L43/12

Abstract: A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a selector layer coupled to the first terminal.

公开(公告)号：US11450357B2

公开(公告)日：2022-09-20

申请号：US16943345

申请日：2020-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ku-Feng Lin ,  Hiroki Noguchi

IPC: G11C11/00 ,  G11C7/06 ,  G11C13/00 ,  G11C11/16

Abstract: A memory device is provided and includes multiple memory cells, multiple reference cells, and multiple sense amplifiers. The memory cells are coupled to first inputs of the sense amplifiers, respectively. The reference cells are coupled to second inputs of the sense amplifiers, respectively. The reference cells are coupled to each other.

公开(公告)号：US20240315051A1

公开(公告)日：2024-09-19

申请号：US18679002

申请日：2024-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shy-Jay Lin ,  Chien-Min Lee ,  Hiroki Noguchi ,  MingYuan Song ,  Yen-Lin Huang ,  William Joseph Gallagher

IPC: H10B61/00 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H10B61/22 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/528

Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.

公开(公告)号：US12046317B2

公开(公告)日：2024-07-23

申请号：US18314743

申请日：2023-05-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hiroki Noguchi

IPC: G11C29/20 ,  G11C29/00 ,  G11C29/42 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/20 ,  G11C29/44 ,  G11C29/72

Abstract: A memory system is provided. The memory system includes an error correction code circuit configured to correct a maximum of N error bits in each of multiple read data and a monitor circuit configured to monitor multiple fail word addresses associated with M error bits, and further configured to output a first word address in the fail word addresses to replace first memory locations corresponding to the first word address. Each of the fail word addresses corresponds to one of multiple counter values, and the first word address corresponds to a maximum value of the counter values.

公开(公告)号：US11723218B2

公开(公告)日：2023-08-08

申请号：US17216162

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shy-Jay Lin ,  Chien-Min Lee ,  Hiroki Noguchi ,  Mingyuan Song ,  Yen-Lin Huang ,  William Joseph Gallagher

IPC: H01L21/00 ,  H10B61/00 ,  H01L23/528 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H10B61/22 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/528

Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.

公开(公告)号：US11386936B2

公开(公告)日：2022-07-12

申请号：US16925295

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hiroki Noguchi ,  Ku-Feng Lin ,  Yih Wang

IPC: G11C7/02 ,  G11C7/06

Abstract: A memory device for sensing memory cell in a memory array includes at least one first memory cell, a first sensing amplifier, a first multiplexer circuit, a plurality of first reference cells, and a controller. The first sensing amplifier is coupled to the at least one first memory cell. An output terminal of the first multiplexer circuit is coupled to the reference terminal of the first sensing amplifier. Each of the first reference cells is coupled to each input node of the first multiplexer circuit. The controller is coupled to a control terminal of the first multiplexer circuit. The first sensing amplifier comprises an output terminal and a reference terminal. The controller controls the first multiplexer circuit to select one of the first reference cells as a selected reference cell to couple to the reference terminal of the first sensing amplifier when each read operation to the at least one first memory cell is performed.

公开(公告)号：US11237834B2

公开(公告)日：2022-02-01

申请号：US16923107

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hiroki Noguchi ,  Yih Wang

IPC: G06F9/30 ,  G06F11/10

Abstract: A memory device includes a memory array with at least one memory macro, a flag, and a controller. The controller is coupled to the memory array. Each bit of data stored in the at least one memory macro is presented as a first bit type or a second bit type. The controller is configured to select one of a first situation mode and a second situation mode as a selected situation mode according to a first retention time of the first bit type and a second retention time of the second bit type. The first situation mode is that a number of bits with the first bit type in data is larger than a number of bit with the second bit type in data, and the second situation mode is that the number of bit with the first bit type in data is not larger than the number of bits with the second bit type in data. In a write operation of the at least one memory macro, the controller determines that an input data is meet the selected situation mode or not. In response to the input data is meet the selected situation mode, the controller disables the flag and writes the input data into the at least one memory macro. In response to the input data is not meet the selected situation mode, the controller enables the flag, inverts the input data, and writes an inverted input data into the at least one memory macro.

公开(公告)号：US20210272606A1

公开(公告)日：2021-09-02

申请号：US16925295

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hiroki Noguchi ,  Ku-Feng Lin ,  Yih Wang

IPC: G11C7/06

Abstract: A memory device for sensing memory cell in a memory array includes at least one first memory cell, a first sensing amplifier, a first multiplexer circuit, a plurality of first reference cells, and a controller. The first sensing amplifier is coupled to the at least one first memory cell. An output terminal of the first multiplexer circuit is coupled to the reference terminal of the first sensing amplifier. Each of the first reference cells is coupled to each input node of the first multiplexer circuit. The controller is coupled to a control terminal of the first multiplexer circuit. the first sensing amplifier comprises an output terminal and a reference terminal. The controller controls the first multiplexer circuit to select one of the first reference cells as a selected reference cell to couple to the reference terminal of the first sensing amplifier when each read operation to the at least one first memory cell is performed.