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公开(公告)号：US11373690B2
公开(公告)日：2022-06-28
申请号：US17156383
申请日：2021-01-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ku-Feng Lin , Yu-Der Chih , Yi-Chun Shih , Chia-Fu Lee
Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.
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公开(公告)号：US20210312999A1
公开(公告)日：2021-10-07
申请号：US16836928
申请日：2020-04-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hiroki Noguchi , Ku-Feng Lin , Yih Wang
Abstract: A testing device for memory includes a memory array and a test apparatus. The test apparatus includes a controller and a pattern generator. The pattern generator generates a background data, a first pattern data, and a second pattern data. The controller sets up the background data to a to-be-tested memory sub-array of the memory sub-arrays, performs a first memory test operation with the to-be-tested memory sub-array according to the first pattern data for detecting whether the hardware failure of the to-be-tested memory sub-array is occurred during the first memory test operation. The controller performs a second memory test operation with the to-be-tested memory sub-array according to the second pattern data for detecting whether the hardware failure of the to-be-tested memory sub-array is occurred during the second memory test operation in response to the hardware failure of the to-be-tested memory sub-array is not occurred during the first memory test operation.
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3.发明授权Accommodating balance of bit line and source line resistances in magnetoresistive random access memory 有权适应磁阻随机存取存储器中位线和源极线电阻的平衡公开(公告)号：US08923040B2
公开(公告)日：2014-12-30
申请号：US13753569
申请日：2013-01-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Kai-Chun Lin , Hung-Chang Yu , Ku-Feng Lin , Yue-Der Chih
CPC classification number: G11C11/1675 , G11C7/12 , G11C7/14 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1697
Abstract: A memory has magnetic tunnel junction elements with different resistances in different logic states, for bit positions in memory words accessed by a word line signal coupling each bit cell in the addressed word between a bit line and source line for that bit position. The bit lines and source lines are longer and shorter at different word line locations, causing a resistance body effect. A clamping transistor couples the bit line to a sensing circuit when reading, applying a current through the bit cell and producing a read voltage compared by the sensing circuit to a reference such as a comparable voltage from a reference bit cell circuit having a similar structure. A drive control varies an input to the switching transistor as a function of the word line location, e.g., by word line address, to offset the different bit and source line resistances.
Abstract translation: 存储器具有在不同逻辑状态下具有不同电阻的磁性隧道结元件，对于通过字线信号访问的位线信号中的位位置，该位线信号将寻址字中的每个位单元耦合在该位位置的位线和源极线之间。 位线和源极线在不同的字线位置越来越短，从而产生电阻体效应。 当读取电流时，钳位晶体管将位线耦合到感测电路，通过位单元施加电流，并将由感测电路比较的读取电压产生为诸如具有类似结构的参考位单元电路的可比电压的参考。 驱动控制通过例如字线地址改变作为字线位置的函数的开关晶体管的输入，以偏移不同的位和源极线电阻。
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公开(公告)号：US11183261B2
公开(公告)日：2021-11-23
申请号：US16836928
申请日：2020-04-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hiroki Noguchi , Ku-Feng Lin , Yih Wang
Abstract: A testing device for memory includes a memory array and a test apparatus. The test apparatus includes a controller and a pattern generator. The pattern generator generates a background data, a first pattern data, and a second pattern data. The controller sets up the background data to a to-be-tested memory sub-array of the memory sub-arrays, performs a first memory test operation with the to-be-tested memory sub-array according to the first pattern data for detecting an occurrence of a hardware failure of the to-be-tested memory sub-array is occurred during the first memory test operation. The controller performs a second memory test operation with the to-be-tested memory sub-array according to the second pattern data for detecting the occurrence of the hardware failure of the to-be-tested memory sub-array during the second memory test operation in response to the hardware failure of the to-be-tested memory sub-array is not occurred during the first memory test operation.
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公开(公告)号：US10163980B2
公开(公告)日：2018-12-25
申请号：US15165925
申请日：2016-05-26
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Ku-Feng Lin , Hung-Chang Yu , Kai-Chun Lin , Yu-Der Chih
IPC: H01L27/24 , H01L45/00 , H01L23/48 , H01L23/522 , H01L23/528 , H01L25/18 , H01L27/088 , H01L23/532
Abstract: A method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure.
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Patent Agency Ranking
公开(公告)号：US09330746B2
公开(公告)日：2016-05-03
申请号：US14219350
申请日：2014-03-19
Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
Inventor： Kai-Chun Lin , Hung-Chang Yu , Ku-Feng Lin , Yue-Der Chih
CPC classification number: G11C11/1655 , G11C11/1659 , G11C11/1675 , G11C11/1697 , G11C13/0026 , G11C13/0069 , G11C2013/0083 , G11C2213/79 , G11C2213/82
Abstract: A circuit that includes a current source module, a current sink module and a memory bank is disclosed. Each of the current source module, the current sink module and the memory bank is connected to the first bit/source line and the second bit/source line. The memory bank is bounded by the current source module and the current sink module. When the current source module and the current sink module receive a triggering pulse from the first bit/source line and a select signal with a first state, the current source module is activated to generate an operating current to the first bit/source line that transmits through a conducted memory cell of the memory bank and the current sink module is activated to drain the operating current from the second bit/source line.
Abstract translation: 公开了一种包括电流源模块，电流吸收模块和存储体的电路。 电流源模块，电流模块和存储器组中的每一个都连接到第一位/源极线和第二位/源极线。 存储体由当前的源模块和当前的模块组成。 当电流源模块和电流接收模块从第一位/源线接收到触发脉冲和具有第一状态的选择信号时，电流源模块被激活以产生到第一位/源线的工作电流， 通过存储体的传导存储单元并且激活电流吸收模块以从第二位/源极线中漏去工作电流。
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公开(公告)号：US11450357B2
公开(公告)日：2022-09-20
申请号：US16943345
申请日：2020-07-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Ku-Feng Lin , Hiroki Noguchi
Abstract: A memory device is provided and includes multiple memory cells, multiple reference cells, and multiple sense amplifiers. The memory cells are coupled to first inputs of the sense amplifiers, respectively. The reference cells are coupled to second inputs of the sense amplifiers, respectively. The reference cells are coupled to each other.
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公开(公告)号：US10366765B2
公开(公告)日：2019-07-30
申请号：US15635887
申请日：2017-06-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Der Chih , Hung-Chang Yu , Ku-Feng Lin
Abstract: The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.
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公开(公告)号：US12125551B2
公开(公告)日：2024-10-22
申请号：US17874973
申请日：2022-07-27
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Ku-Feng Lin , Hiroki Noguchi
CPC classification number: G11C7/062 , G11C11/16 , G11C13/004
Abstract: A memory device includes a plurality of sense amplifiers, a plurality of memory cells, a plurality of data lines, a plurality of reference cells, and a connection line. The memory cells are coupled to a plurality of first inputs of the plurality of sense amplifiers respectively. The data lines are coupled to a plurality of second inputs of the plurality of sense amplifiers respectively. The reference cells are arranged in a plurality of columns respectively and coupled to the plurality of data line respectively. Each of the plurality of reference cells includes a plurality of resistive elements. The connection line is coupled to the plurality of data lines. In a read mode, one of the sense amplifiers is configured to access the plurality of resistive elements arranged in at least one of the plurality of columns.
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公开(公告)号：US12080375B2
公开(公告)日：2024-09-03
申请号：US18232768
申请日：2023-08-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ku-Feng Lin , Yu-Der Chih , Yi-Chun Shih , Chia-Fu Lee
CPC classification number: G11C7/065 , G11C7/08 , G11C11/14 , G11C13/004 , H01L27/10
Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.
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