公开(公告)号：US20200373732A1

公开(公告)日：2020-11-26

申请号：US16417712

申请日：2019-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Bin Chen ,  Ming Chyi Liu

IPC: H01S5/022

Abstract: Various embodiments of the present disclosure are directed towards a vertical cavity surface emitting laser (VCSEL) device. The VCSEL device includes a bond bump overlying a substrate. A VCSEL structure overlies the bond bump. The VCSEL structure includes a second reflector overlying an optically active region and a first reflector underlying the optically active region. A bond ring overlying the substrate and laterally separated from the bond bump. The bond ring continuously extends around the bond bump.

公开(公告)号：US11329128B2

公开(公告)日：2022-05-10

申请号：US16921075

申请日：2020-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Bin Chen ,  Ming Chyi Liu

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/08

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate and a drain region disposed within the substrate. The drain region is separated from the source region along a first direction. A drift region is disposed within the substrate between the source region and the drain region, and a plurality of isolation structures are disposed within the drift region. A gate electrode is disposed within the substrate. The gate electrode has a base region disposed between the source region and the drift region and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of isolation structures.

公开(公告)号：US11025033B2

公开(公告)日：2021-06-01

申请号：US16417712

申请日：2019-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Bin Chen ,  Ming Chyi Liu

IPC: H01S5/183 ,  H01S5/02375 ,  H01S5/42 ,  H01S5/0237 ,  H01S5/30

Abstract: Various embodiments of the present disclosure are directed towards a vertical cavity surface emitting laser (VCSEL) device. The VCSEL device includes a bond bump overlying a substrate. A VCSEL structure overlies the bond bump. The VCSEL structure includes a second reflector overlying an optically active region and a first reflector underlying the optically active region. A bond ring overlying the substrate and laterally separated from the bond bump. The bond ring continuously extends around the bond bump.

公开(公告)号：US20210091538A1

公开(公告)日：2021-03-25

申请号：US16579692

申请日：2019-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Bin Chen ,  Ming Chyi Liu

IPC: H01S5/183

Abstract: In some embodiments, the present disclosure relates to a vertical cavity surface emitting laser (VCSEL) device that includes a microlens arranged over a reflector stack. The reflector stack comprises alternating reflector layers of a first material and a second material. The microlens stack includes a first lens layer, a second lens layer arranged over the first lens layer, and a third lens layer arranged over the second lens layer. The first lens layer comprises a first average concentration of a first element and has a first width. The second lens layer comprises a second average concentration of the first element greater than the first average concentration and has a second width smaller than the first width. The third lens layer comprises a third average concentration of the first element greater than the second average concentration and has a third width smaller than the second width.

公开(公告)号：US20200076162A1

公开(公告)日：2020-03-05

申请号：US16122018

申请日：2018-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen Yu Chen ,  Ming Chyi Liu ,  Jhih-Bin Chen

IPC: H01S5/183 ,  H01S5/02 ,  H01S5/187 ,  H01S5/20 ,  H01S5/028

Abstract: Some embodiments relate to a method for manufacturing a vertical cavity surface emitting laser. The method includes forming an optically active layer over a first reflective layer and forming a second reflective layer over the optically active layer. Forming a masking layer over the second reflective layer, where the masking layer leaves a sacrificial portion of the second reflective layer exposed. A first etch is performed to remove the sacrificial portion of the second reflective layer, defining a second reflector. Forming a first spacer covering outer sidewalls of the second reflector and masking layer. An oxidation process is performed with the first spacer in place to oxidize a peripheral region of the optically active layer while leaving a central region of the optically active layer un-oxidized. A second etch is performed to remove a portion of the oxidized peripheral region, defining an optically active region. Forming a second spacer covering outer sidewalls of the first spacer, the optically active region, and the first reflector.

公开(公告)号：US20200006271A1

公开(公告)日：2020-01-02

申请号：US16025046

申请日：2018-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Bin Chen ,  Chia-Shiung Tsai ,  Ming Chyi Liu ,  Eugene Chen

IPC: H01L23/00 ,  H01S5/183 ,  H01S5/343 ,  H01S5/022

Abstract: Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.