公开(公告)号：US20210074551A1

公开(公告)日：2021-03-11

申请号：US16567290

申请日：2019-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Chen-Hao Chiang ,  Alexander Kalnitsky ,  Yeur-Luen Tu ,  Eugene Chen

IPC: H01L21/322 ,  H01L23/66 ,  H01L29/06 ,  H01L29/34 ,  H01L21/762

Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.

公开(公告)号：US11164844B2

公开(公告)日：2021-11-02

申请号：US16568605

申请日：2019-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen Yu Chen ,  Ming Chyi Liu ,  Eugene Chen

IPC: H01L23/00 ,  H01L33/00 ,  H01L33/62 ,  H01S5/18 ,  H01L25/075

Abstract: In some embodiments, the present disclosure relates to a method of forming a package assembly. A wet etch stop layer is formed over a frontside of a semiconductor substrate. A sacrificial semiconductor layer is formed over the wet etch stop layer, and a dry etch stop layer is formed over the sacrificial semiconductor layer. A stack of semiconductor device layers may be formed over the dry etch stop layer. A bonding process is performed to bond the stack of semiconductor device layers to a frontside of an integrated circuit die, wherein the frontside of the semiconductor substrate faces the frontside of the integrated circuit die. A wet etching process is performed to remove the semiconductor substrate, and a dry etching process is performed to remove the wet etch stop layer and the sacrificial semiconductor layer.

公开(公告)号：US10134945B1

公开(公告)日：2018-11-20

申请号：US15688200

申请日：2017-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Chen-Hua Yu ,  Chia-Shiung Tsai ,  Alexander Kalnitsky ,  Ru-Liang Lee ,  Eugene Chen

IPC: H01L21/30 ,  H01L21/46 ,  H01L33/00 ,  H01L21/762 ,  H01L21/18 ,  H01L21/285 ,  H01L21/8258

Abstract: A method for wafer to wafer bonding for III-V and CMOS wafers is provided. A silicon carrier wafer is provided having an epitaxial III-V semiconductor region and an oxide region disposed over the wafer top surface, the regions having substantially equal heights. A sidewall of the epitaxial III-V semiconductor region directly contacts a sidewall of the oxide region. A eutectic bonding layer is formed over a top surface of the epitaxial III-V semiconductor region and the oxide region for bonding to the CMOS wafer which contains semiconductor devices. The silicon carrier wafer is removed, and the CMOS wafer is singulated to form a plurality of three-dimensional integrated circuits, each including a CMOS substrate corresponding to a portion of the CMOS wafer and a III-V optical device corresponding to a portion of the III-V epitaxial semiconductor region.

公开(公告)号：US11824077B2

公开(公告)日：2023-11-21

申请号：US16952384

申请日：2020-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Eugene Chen

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14636 ,  H01L27/14685

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an epitaxial structure having a group IV chemical element disposed in a semiconductor substrate, where the epitaxial structure extends into the semiconductor substrate from a first side of the semiconductor substrate. A photodetector is at least partially arranged in the epitaxial structure. A first capping structure having a first capping structure chemical element that is different than the first group IV chemical element covers the epitaxial structure on the first side of the semiconductor substrate. A second capping structure is arranged between the first capping structure and the epitaxial structure, where the second capping structure includes the group IV chemical element and the first capping structure chemical element.

公开(公告)号：US20210082866A1

公开(公告)日：2021-03-18

申请号：US16568605

申请日：2019-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen Yu Chen ,  Ming Chyi Liu ,  Eugene Chen

IPC: H01L23/00 ,  H01L25/075 ,  H01L33/00 ,  H01L33/62 ,  H01S5/18

Abstract: In some embodiments, the present disclosure relates to a method of forming a package assembly. A wet etch stop layer is formed over a frontside of a semiconductor substrate. A sacrificial semiconductor layer is formed over the wet etch stop layer, and a dry etch stop layer is formed over the sacrificial semiconductor layer. A stack of semiconductor device layers may be formed over the dry etch stop layer. A bonding process is performed to bond the stack of semiconductor device layers to a frontside of an integrated circuit die, wherein the frontside of the semiconductor substrate faces the frontside of the integrated circuit die. A wet etching process is performed to remove the semiconductor substrate, and a dry etching process is performed to remove the wet etch stop layer and the sacrificial semiconductor layer.

公开(公告)号：US20210074755A1

公开(公告)日：2021-03-11

申请号：US16952384

申请日：2020-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Eugene Chen

IPC: H01L27/146

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an epitaxial structure having a group IV chemical element disposed in a semiconductor substrate, where the epitaxial structure extends into the semiconductor substrate from a first side of the semiconductor substrate. A photodetector is at least partially arranged in the epitaxial structure. A first capping structure having a first capping structure chemical element that is different than the first group IV chemical element covers the epitaxial structure on the first side of the semiconductor substrate. A second capping structure is arranged between the first capping structure and the epitaxial structure, where the second capping structure includes the group IV chemical element and the first capping structure chemical element.

公开(公告)号：US20200006271A1

公开(公告)日：2020-01-02

申请号：US16025046

申请日：2018-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Bin Chen ,  Chia-Shiung Tsai ,  Ming Chyi Liu ,  Eugene Chen

IPC: H01L23/00 ,  H01S5/183 ,  H01S5/343 ,  H01S5/022

Abstract: Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.

公开(公告)号：US11171015B2

公开(公告)日：2021-11-09

申请号：US16567290

申请日：2019-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Chen-Hao Chiang ,  Alexander Kalnitsky ,  Yeur-Luen Tu ,  Eugene Chen

IPC: H01L21/322 ,  H01L23/66 ,  H01L21/762 ,  H01L29/34 ,  H01L29/06

Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.

公开(公告)号：US11158593B2

公开(公告)日：2021-10-26

申请号：US16829267

申请日：2020-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Bin Chen ,  Chia-Shiung Tsai ,  Ming Chyi Liu ,  Eugene Chen

IPC: H01L23/12 ,  H01L23/48 ,  H01L21/00 ,  H01L21/28 ,  H01L23/00 ,  H01S5/183 ,  H01S5/343 ,  H01S5/0234 ,  H01S5/02355 ,  H01L25/075 ,  H01L33/46 ,  H01L25/065

Abstract: Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.

公开(公告)号：US10861896B2

公开(公告)日：2020-12-08

申请号：US16047455

申请日：2018-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Eugene Chen

IPC: H01L27/146

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an epitaxial structure having a group IV chemical element disposed in a semiconductor substrate, where the epitaxial structure extends into the semiconductor substrate from a first side of the semiconductor substrate. A photodetector is at least partially arranged in the epitaxial structure. A first capping structure having a first capping structure chemical element that is different than the first group IV chemical element covers the epitaxial structure on the first side of the semiconductor substrate. A second capping structure is arranged between the first capping structure and the epitaxial structure, where the second capping structure includes the group IV chemical element and the first capping structure chemical element.