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    HIGH VOLTAGE DEVICE WITH GATE EXTENSIONS
    2.
    发明申请
    HIGH VOLTAGE DEVICE WITH GATE EXTENSIONS 有权

    公开(公告)号：US20210066451A1

    公开(公告)日：2021-03-04

    申请号：US16921075

    申请日：2020-07-06

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jhih-Bin Chen ,  Ming Chyi Liu

    IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78

    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate and a drain region disposed within the substrate. The drain region is separated from the source region along a first direction. A drift region is disposed within the substrate between the source region and the drain region, and a plurality of isolation structures are disposed within the drift region. A gate electrode is disposed within the substrate. The gate electrode has a base region disposed between the source region and the drift region and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of isolation structures.

    STRUCTURES FOR BONDING A GROUP III-V DEVICE TO A SUBSTRATE BY STACKED CONDUCTIVE BUMPS
    3.
    发明申请
    STRUCTURES FOR BONDING A GROUP III-V DEVICE TO A SUBSTRATE BY STACKED CONDUCTIVE BUMPS 审中-公开

    公开(公告)号：US20200227369A1

    公开(公告)日：2020-07-16

    申请号：US16829267

    申请日：2020-03-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jhih-Bin Chen ,  Chia-Shiung Tsai ,  Ming Chyi Liu ,  Eugene Chen

    IPC: H01L23/00 ,  H01S5/022 ,  H01S5/183 ,  H01S5/343

    Abstract: Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.

    VCSEL with self-aligned microlens to improve beam divergence
    8.
    发明授权
    VCSEL with self-aligned microlens to improve beam divergence 有权

    公开(公告)号：US11437785B2

    公开(公告)日：2022-09-06

    申请号：US16579692

    申请日：2019-09-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jhih-Bin Chen ,  Ming Chyi Liu

    IPC: H01S5/183 ,  H01S5/0239 ,  H01S5/02335 ,  H01S5/02

    Abstract: A vertical cavity surface emitting laser (VCSEL) device includes a microlens arranged over a reflector stack. The reflector stack includes alternating reflector layers of a first material and a second material. The microlens stack includes a first lens layer, a second lens layer arranged over the first lens layer, and a third lens layer arranged over the second lens layer. The first lens layer includes a first average concentration of a first element and has a first width. The second lens layer includes a second average concentration of the first element greater than the first average concentration and has a second width smaller than the first width. The third lens layer includes a third average concentration of the first element greater than the second average concentration and has a third width smaller than the second width.

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