公开(公告)号：US20180350586A1

公开(公告)日：2018-12-06

申请号：US16045576

申请日：2018-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jin Cai

IPC: H01L21/02 ,  H01G4/018 ,  H01L31/113 ,  H01L29/66 ,  H01L27/088 ,  H01L33/00

CPC classification number: H01L21/02019 ,  H01G4/018 ,  H01L27/0886 ,  H01L29/6659 ,  H01L31/113 ,  H01L33/0041

Abstract: A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a semiconductor substrate; a fin extending from the semiconductor substrate; a first charged dielectric layer covering a bottom portion of the fin, the first charged dielectric layer having net fixed first-type charges; a second charged dielectric layer covering the first charged dielectric layer, the second charged dielectric layer having net fixed second-type charges, the second-type charges being opposite to the first-type charges; and a gate structure engaging a top portion of the fin.

公开(公告)号：US20180350585A1

公开(公告)日：2018-12-06

申请号：US15609775

申请日：2017-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jin Cai

IPC: H01L21/02 ,  H01L27/088 ,  H01L29/66 ,  H01L33/00 ,  H01L31/113 ,  H01G4/018

CPC classification number: H01L21/02019 ,  H01G4/018 ,  H01L27/0886 ,  H01L29/6659 ,  H01L31/113 ,  H01L33/0041

Abstract: A semiconductor device and a method of forming the same are disclosed. The method includes receiving a semiconductor substrate and a fin extending from the semiconductor substrate; forming multiple dielectric layers conformally covering the fin, the multiple dielectric layers including a first charged dielectric layer having net fixed first-type charges and a second charged dielectric layer having net fixed second-type charges, the second-type charges being opposite to the first-type charges, the first-type charges having a first sheet density and the second-type charges having a second sheet density, the first charged dielectric layer being interposed between the fin and the second charged dielectric layer; patterning the multiple dielectric layers, thereby exposing a first portion of the fin, wherein a second portion of the fin is surrounded by at least a portion of the first charged dielectric layer; and forming a gate structure engaging the first portion of the fin.

公开(公告)号：US12170323B2

公开(公告)日：2024-12-17

申请号：US18365995

申请日：2023-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Yi-Tse Hung ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li ,  Jin Cai

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

公开(公告)号：US20240072052A1

公开(公告)日：2024-02-29

申请号：US18151279

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Yi-Bo Liao ,  Jin Cai

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823871

Abstract: In an embodiment, a device includes: a dielectric wall; nanostructures abutting the dielectric wall; a lower source/drain region adjoining a lower subset of the nanostructures; an upper source/drain region adjoining an upper subset of the nanostructures, the upper source/drain region oppositely doped from the lower source/drain region; and a shared source/drain contact contacting the upper source/drain region and the lower source/drain region, the shared source/drain contact extending into the dielectric wall.

公开(公告)号：US20230380257A1

公开(公告)日：2023-11-23

申请号：US18366000

申请日：2023-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jin Cai ,  Sheng-Kai Su

IPC: H10K85/20 ,  H01L21/02 ,  H01L29/06 ,  H10K10/46

CPC classification number: H10K85/221 ,  H01L21/02606 ,  H01L29/0673 ,  H10K10/472 ,  H10K10/474 ,  H10K10/484

Abstract: A method includes depositing a dielectric layer over a substrate, forming carbon nanotubes on the dielectric layer, forming a dummy gate stack on the carbon nanotubes, forming gate spacers on opposing sides of the dummy gate stack, and removing the dummy gate stack to form a trench between the gate spacers. The carbon nanotubes are exposed to the trench. The method further includes etching a portion of the dielectric layer underlying the carbon nanotubes, with the carbon nanotubes being suspended, forming a replacement gate dielectric surrounding the carbon nanotubes, and forming a gate electrode surrounding the replacement gate dielectric.

公开(公告)号：US20220367718A1

公开(公告)日：2022-11-17

申请号：US17874466

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Ho ,  Ming-Shiang Lin ,  Jin Cai

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66

Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.

公开(公告)号：US20220359736A1

公开(公告)日：2022-11-10

申请号：US17874377

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Kai Su ,  Jin Cai

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/24

Abstract: A method includes etching a dielectric layer to form a dielectric fin, depositing a transition metal dichalcogenide layer on the dielectric fin, and performing an anisotropic etching process on the transition metal dichalcogenide layer. Horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain to form a vertical semiconductor ring. The method further includes forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring, and forming a source/drain contact plug, wherein the source/drain contact plug contacts sidewalls of a second portion of the vertical semiconductor ring.

公开(公告)号：US11189726B2

公开(公告)日：2021-11-30

申请号：US16874539

申请日：2020-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng Yuan ,  Ming-Shiang Lin ,  Chia-Cheng Ho ,  Jin Cai ,  Tzu-Chung Wang ,  Tung Ying Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8234

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

公开(公告)号：US11145676B1

公开(公告)日：2021-10-12

申请号：US16880998

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Chih-Sheng Chang ,  Tzu-Chiang Chen ,  Jin Cai

IPC: G11C11/22 ,  H01L27/11597 ,  H01L43/08 ,  G11C11/16

Abstract: A memory device includes a plurality of word lines, a plurality of bit lines, a plurality of source lines and a plurality of multi-level memory cells is introduced. Each of the multi-level memory cells is coupled to one of the word lines, one of the bit lines and one of the source lines. Each of the multi-level memory cells includes a ferroelectric storage element and a magneto-resistive storage element cascaded to the ferroelectric storage element. The ferroelectric storage element is configured to store a first bit of a multi-bit data. The magneto-resistive storage element is configured to store a second bit of the multi-bit data.

公开(公告)号：US10707347B2

公开(公告)日：2020-07-07

申请号：US16255334

申请日：2019-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng Yuan ,  Chia-Cheng Ho ,  Tzu-Chung Wang ,  Tung Ying Lee ,  Jin Cai ,  Ming-Shiang Lin

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/78

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.