公开(公告)号：US20240363152A1

公开(公告)日：2024-10-31

申请号：US18767858

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ku-Feng LIN ,  Yu-Der CHIH ,  Yi-Chun SHIH ,  Chia-Fu LEE

IPC: G11C7/06 ,  G11C7/08 ,  G11C11/14 ,  G11C13/00 ,  H01L27/10

CPC classification number: G11C7/065 ,  G11C7/08 ,  G11C11/14 ,  G11C13/004 ,  H01L27/10

Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

公开(公告)号：US20220262409A1

公开(公告)日：2022-08-18

申请号：US17737734

申请日：2022-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ku-Feng LIN ,  Yu-Der CHIH ,  Yi-Chun SHIH ,  Chia-Fu LEE

IPC: G11C7/06 ,  G11C7/08 ,  G11C13/00 ,  G11C11/14

Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

公开(公告)号：US20180308554A1

公开(公告)日：2018-10-25

申请号：US16023393

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Der CHIH ,  Hung-Chang YU ,  Ku-Feng LIN

IPC: G11C16/28 ,  G11C16/08

CPC classification number: G11C16/28 ,  G11C16/08

Abstract: The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.

公开(公告)号：US20160268344A1

公开(公告)日：2016-09-15

申请号：US15165925

申请日：2016-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ku-Feng LIN ,  Hung-Chang YU ,  Kai-Chun LIN ,  Yu-Der CHIH

IPC: H01L27/24 ,  H01L23/528 ,  H01L27/088 ,  H01L23/48 ,  H01L25/18 ,  H01L45/00 ,  H01L23/522

CPC classification number: H01L27/2463 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L25/18 ,  H01L27/088 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1641 ,  H01L45/1683

Abstract: The present disclosure provides a method of fabricating a resistive memory array. In one embodiment, a method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure.