中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.018 seconds)

    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER
    2.
    发明公开
    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER 审中-公开

    公开(公告)号：US20240363152A1

    公开(公告)日：2024-10-31

    申请号：US18767858

    申请日：2024-07-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ku-Feng LIN ,  Yu-Der CHIH ,  Yi-Chun SHIH ,  Chia-Fu LEE

    IPC: G11C7/06 ,  G11C7/08 ,  G11C11/14 ,  G11C13/00 ,  H01L27/10

    CPC classification number: G11C7/065 ,  G11C7/08 ,  G11C11/14 ,  G11C13/004 ,  H01L27/10

    Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER
    3.
    发明申请
    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER 有权

    公开(公告)号：US20220262409A1

    公开(公告)日：2022-08-18

    申请号：US17737734

    申请日：2022-05-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ku-Feng LIN ,  Yu-Der CHIH ,  Yi-Chun SHIH ,  Chia-Fu LEE

    IPC: G11C7/06 ,  G11C7/08 ,  G11C13/00 ,  G11C11/14

    Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

    DEVICE AND METHOD FOR DATA-WRITING
    4.
    发明申请
    DEVICE AND METHOD FOR DATA-WRITING 有权

    公开(公告)号：US20210174841A1

    公开(公告)日：2021-06-10

    申请号：US17183215

    申请日：2021-02-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Po-Hao LEE ,  Yi-Chun SHIH

    IPC: G11C5/14 ,  G11C7/14 ,  G11C16/30 ,  G11C13/00 ,  G11C29/56

    Abstract: A device includes several first switching units and several second switching units. Each of the first switching units transmits in response to a first select signal, an auxiliary signal. Each of the second switching units is coupled to a corresponding one of the first switching units and transmits in response to a second select signal, a write voltage to a corresponding one of multiple circuit cells. The second switching units are coupled with each other in a node which receives the write voltage.

    MEMORY DEVICE AND REFERENCE CIRCUIT THEREOF
    5.
    发明申请
    MEMORY DEVICE AND REFERENCE CIRCUIT THEREOF 审中-公开

    公开(公告)号：US20170330608A1

    公开(公告)日：2017-11-16

    申请号：US15667600

    申请日：2017-08-02

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chia-Fu LEE ,  Yu-Der CHIH ,  Hon-Jarn LIN ,  Yi-Chun SHIH

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/22 ,  G11C11/161 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2207/063

    Abstract: A device includes memory cells, a reference circuit, and a sensing unit. The reference circuit includes a first reference switch, a second reference switch, and reference storage units. The first reference switch is turned on when a reference word line is activated. The second reference switch is turned on when the reference word line is activated. The reference storage units include a first reference storage unit and a second reference storage unit. The first reference storage unit generates a first signal having a first logic state when the first reference switch is turned on. The second reference storage unit generates a second signal having a second logic state when the second reference switch is turned on. The sensing unit determines a logic state of the bit data of one of the memory cells according to the first signal and the second signal.

    METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORK
    6.
    发明申请
    METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORK 有权

    公开(公告)号：US20250117642A1

    公开(公告)日：2025-04-10

    申请号：US18983284

    申请日：2024-12-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Win-San KHWA ,  Yu-Der CHIH ,  Yi-Chun SHIH ,  Chien-Yin LIU

    IPC: G06N3/063 ,  G06N3/08 ,  G11C7/10 ,  G11C11/54 ,  G11C29/04

    Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.

    DEVICE AND METHOD FOR DATA-WRITING
    7.
    发明申请
    DEVICE AND METHOD FOR DATA-WRITING 审中-公开

    公开(公告)号：US20190019541A1

    公开(公告)日：2019-01-17

    申请号：US16133283

    申请日：2018-09-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Po-Hao LEE ,  Yi-Chun SHIH

    IPC: G11C5/14 ,  G11C16/30 ,  G11C29/56 ,  G11C7/14 ,  G11C13/00 ,  G11C29/50

    Abstract: A device includes a circuit cell, a voltage regulator, a first switching unit, a second switching unit, and a third switching unit. The voltage regulator is configured to output a write voltage. The first switching unit is configured to generate, in response to a control voltage, a current represented by an auxiliary signal. The second switching unit is configured to receive the auxiliary signal, and to turn on to transmit the auxiliary signal to the circuit cell. The third switching unit is configured to receive the write voltage, and to turn on to transmit the write voltage to the circuit cell.

    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER
    9.
    发明公开
    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER 审中-公开

    公开(公告)号：US20230386528A1

    公开(公告)日：2023-11-30

    申请号：US18232768

    申请日：2023-08-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ku-Feng LIN ,  Yu-Der CHIH ,  Yi-Chun SHIH ,  Chia-Fu LEE

    IPC: G11C7/06 ,  G11C7/08 ,  G11C13/00 ,  G11C11/14

    CPC classification number: G11C7/065 ,  G11C7/08 ,  G11C13/004 ,  G11C11/14 ,  H01L27/10

    Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

Patent Agency Ranking