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    METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORK
    1.
    发明申请
    METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORK 有权

    公开(公告)号：US20250117642A1

    公开(公告)日：2025-04-10

    申请号：US18983284

    申请日：2024-12-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Win-San KHWA ,  Yu-Der CHIH ,  Yi-Chun SHIH ,  Chien-Yin LIU

    IPC: G06N3/063 ,  G06N3/08 ,  G11C7/10 ,  G11C11/54 ,  G11C29/04

    Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.

    MEMORY WITH SYMMETRIC READ CURRENT PROFILE AND READ METHOD THEREOF
    4.
    发明申请
    MEMORY WITH SYMMETRIC READ CURRENT PROFILE AND READ METHOD THEREOF 审中-公开

    公开(公告)号：US20200302998A1

    公开(公告)日：2020-09-24

    申请号：US16895069

    申请日：2020-06-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yuhsiang CHEN ,  Shao-Yu CHOU ,  Chun-Hao CHANG ,  Min-Shin WU ,  Yu-Der CHIH

    IPC: G11C11/419 ,  G11C11/418

    Abstract: Memories are provided. A memory includes a first memory array, a second memory array, and a read circuit. The first memory array is configured to store main data. The second memory array is configured to store complement data that is complementary to the main data. The read circuit includes a first sense amplifier, a second sense amplifier and an output buffer. The first sense amplifier is configured to provide a first sensing signal according to a reference signal and first data of the main data corresponding to a first address signal. The second sense amplifier is configured to provide a second sensing signal according to the reference signal and second data of the complement data corresponding to the first address signal. The output buffer is configured to provide one of the first sensing signal and the second sensing signal as an output according to a control signal.

    RESISTIVE RANDOM ACCESS MEMORY DEVICE
    5.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY DEVICE 审中-公开

    公开(公告)号：US20190164606A1

    公开(公告)日：2019-05-30

    申请号：US16158498

    申请日：2018-10-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Der CHIH ,  Chung-Cheng Chou ,  Wen-Ting Chu

    IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER
    9.
    发明公开
    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER 审中-公开

    公开(公告)号：US20240363152A1

    公开(公告)日：2024-10-31

    申请号：US18767858

    申请日：2024-07-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ku-Feng LIN ,  Yu-Der CHIH ,  Yi-Chun SHIH ,  Chia-Fu LEE

    IPC: G11C7/06 ,  G11C7/08 ,  G11C11/14 ,  G11C13/00 ,  H01L27/10

    CPC classification number: G11C7/065 ,  G11C7/08 ,  G11C11/14 ,  G11C13/004 ,  H01L27/10

    Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER
    10.
    发明申请
    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER 有权

    公开(公告)号：US20220262409A1

    公开(公告)日：2022-08-18

    申请号：US17737734

    申请日：2022-05-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ku-Feng LIN ,  Yu-Der CHIH ,  Yi-Chun SHIH ,  Chia-Fu LEE

    IPC: G11C7/06 ,  G11C7/08 ,  G11C13/00 ,  G11C11/14

    Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

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