公开(公告)号：US20190237134A1

公开(公告)日：2019-08-01

申请号：US16376198

申请日：2019-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Yen-Huei Chen ,  Mahmut Sinangil

IPC: G11C11/412 ,  G11C8/14 ,  H01L27/11 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/412 ,  G11C8/14 ,  G11C11/418 ,  G11C11/419 ,  H01L27/1104

Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.

公开(公告)号：US20170345485A1

公开(公告)日：2017-11-30

申请号：US15162711

申请日：2016-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mahmut Sinangil ,  Hidehiro Fujiwara ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yen-Huei Chen ,  Sahil Preet Singh

IPC: G11C11/419 ,  G11C8/12 ,  G11C7/16 ,  G11C7/18 ,  G11C11/412 ,  G11C8/16

CPC classification number: G11C11/419 ,  G11C7/16 ,  G11C7/18 ,  G11C8/12 ,  G11C8/16 ,  G11C11/412 ,  G11C2207/005

Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

公开(公告)号：US10510403B2

公开(公告)日：2019-12-17

申请号：US16211589

申请日：2018-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mahmut Sinangil ,  Hidehiro Fujiwara ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yen-Huei Chen ,  Sahil Preet Singh

IPC: G11C11/00 ,  G11C11/419 ,  G11C8/12 ,  G11C11/412 ,  G11C7/16 ,  G11C8/16 ,  G11C7/18

Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

公开(公告)号：US10276231B2

公开(公告)日：2019-04-30

申请号：US15888517

申请日：2018-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Yen-Huei Chen ,  Mahmut Sinangil

IPC: G11C11/412 ,  H01L27/11 ,  G11C11/419 ,  G11C11/418 ,  G11C8/14

Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.

公开(公告)号：US10153038B2

公开(公告)日：2018-12-11

申请号：US15911824

申请日：2018-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mahmut Sinangil ,  Hidehiro Fujiwara ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yen-Huei Chen ,  Sahil Preet Singh

IPC: G11C11/00 ,  G11C11/419 ,  G11C8/12 ,  G11C11/412 ,  G11C7/16 ,  G11C8/16 ,  G11C7/18

Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

公开(公告)号：US20180197601A1

公开(公告)日：2018-07-12

申请号：US15911824

申请日：2018-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mahmut Sinangil ,  Hidehiro Fujiwara ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yen-Huei Chen ,  Sahil Preet Singh

IPC: G11C11/419 ,  G11C11/412 ,  G11C8/16 ,  G11C7/16 ,  G11C7/18 ,  G11C8/12

CPC classification number: G11C11/419 ,  G11C7/16 ,  G11C7/18 ,  G11C8/12 ,  G11C8/16 ,  G11C11/412 ,  G11C2207/005

Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

公开(公告)号：US09922700B2

公开(公告)日：2018-03-20

申请号：US15162711

申请日：2016-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mahmut Sinangil ,  Hidehiro Fujiwara ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yen-Huei Chen ,  Sahil Preet Singh

IPC: G11C11/00 ,  G11C11/419 ,  G11C8/12 ,  G11C11/412 ,  G11C7/16 ,  G11C8/16 ,  G11C7/18

CPC classification number: G11C11/419 ,  G11C7/16 ,  G11C7/18 ,  G11C8/12 ,  G11C8/16 ,  G11C11/412 ,  G11C2207/005

Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

公开(公告)号：US09886996B2

公开(公告)日：2018-02-06

申请号：US15222914

申请日：2016-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Yen-Huei Chen ,  Mahmut Sinangil

IPC: G11C11/412 ,  G11C11/418 ,  H01L27/11 ,  G11C11/419 ,  G11C8/14

CPC classification number: G11C11/412 ,  G11C8/14 ,  G11C11/418 ,  G11C11/419 ,  H01L27/1104

Abstract: In some embodiments, the present disclosure relates to a static random access memory (SRAM) device. The SRAM device includes a plurality of SRAM cells arranged in a plurality of rows and a plurality of columns, wherein respective SRAM cells include respective pairs of complementary data storage nodes to store respective data states. A first pair of access transistors is coupled to the complementary data storage nodes of an SRAM cell and is configured to selectively couple the complementary data storage nodes to a first pair of complementary bitlines, respectively. A second pair of access transistors is coupled to the complementary data storage nodes of the SRAM cell and is configured to selectively couple the complementary data storage nodes to a second pair of complementary bitlines, respectively.