公开(公告)号：US10147609B2

公开(公告)日：2018-12-04

申请号：US15475826

申请日：2017-03-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Chin Chen ,  Cheng-Yi Wu ,  Yu-Hung Cheng ,  Ren-Hua Guo ,  Hsiang Liu ,  Chin-Szu Lee

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/20 ,  H01L29/66 ,  H01L29/04

摘要： A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

公开(公告)号：US20180175196A1

公开(公告)日：2018-06-21

申请号：US15475826

申请日：2017-03-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Chin Chen ,  Cheng-Yi Wu ,  Yu-Hung Cheng ,  Ren-Hua Guo ,  Hsiang Liu ,  Chin-Szu Lee

IPC分类号： H01L29/78 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L21/768

CPC分类号： H01L21/2022 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/30608 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66287 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.