-
公开(公告)号：US10916305B2
公开(公告)日：2021-02-09
申请号：US16654748
申请日：2019-10-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Lien Linus Lu , Yu-Der Chih , Chung-Cheng Chou , Tong-Chern Ong
Abstract: A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state; a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state; and an encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit.
-
公开(公告)号：US20200091425A1
公开(公告)日：2020-03-19
申请号：US16693946
申请日：2019-11-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wen-Ting Chu , Tong-Chern Ong , Ying-Lang Wang
IPC: H01L45/00
Abstract: The present disclosure, in some embodiments, relates to a method of forming a resistive random access memory (RRAM) device. The method includes forming one or more bottom electrode films over a lower interconnect layer within a lower inter-level dielectric layer. A data storage film having a variable resistance is formed above the one or more bottom electrode films. A lower top electrode film including a metal is over the data storage film, one or more oxygen barrier films are over the lower top electrode film, and an upper top electrode film including a metal nitride is formed over the one or more oxygen barrier films The one or more oxygen barrier films include one or more of a metal oxide film and a metal oxynitride film. The upper top electrode film is formed to be completely confined over a top surface of the one or more oxygen barrier films.
-
公开(公告)号：US20200058858A1
公开(公告)日：2020-02-20
申请号：US16662422
申请日：2019-10-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wen-Ting Chu , Tong-Chern Ong , Ying-Lang Wang
IPC: H01L45/00
Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a bottom electrode that is disposed over a lower interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A data storage structure is arranged over the bottom electrode and a multi-layer top electrode is disposed over the data storage structure. The multi-layer top electrode includes conductive top electrode layers separated by an oxygen barrier structure that is configured to mitigate movement of oxygen between the conductive top electrode layers. A sidewall spacer is disposed directly over the bottom electrode and has a sidewall that covers outermost sidewalls of the conductive top electrode layers and the oxygen barrier structure.
-
公开(公告)号：US20200027922A1
公开(公告)日：2020-01-23
申请号：US16583097
申请日：2019-09-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Yang Tsai , Kuo-Ching Huang , Tong-Chern Ong
Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a control device arranged within a substrate and having a terminal. A first memory device is coupled between the terminal of the control device and a first bit-line. A second memory device is coupled between the terminal of the control device and a second bit-line.
-
公开(公告)号：US20200020744A1
公开(公告)日：2020-01-16
申请号：US16583116
申请日：2019-09-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Yang Tsai , Kuo-Ching Huang , Tong-Chern Ong
Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may include forming a control device within a substrate. A first plurality of interconnect layers are formed within a first inter-level dielectric (ILD) structure over the substrate. A first memory device and a second memory device are formed over the first ILD structure. A second plurality of interconnect layers are formed within a second ILD structure over the first ILD structure. The first plurality of interconnect layers and the second plurality of interconnect layers couple the first memory device and the second memory device to the control device.
-
Patent Agency Ranking
公开(公告)号：US20180097173A1
公开(公告)日：2018-04-05
申请号：US15393892
申请日：2016-12-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Harry-Hak-Lay Chuang , Hung Cho Wang , Tong-Chern Ong , Wen-Ting Chu , Yu-Wen Liao , Kuei-Hung Shen , Kuo-Yuan Tu , Sheng-Huang Huang
CPC classification number: H01L43/12 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1675
Abstract: The present disclosure relates to a method of manufacturing a memory device. The method is performed by forming an inter-layer dielectric (ILD) layer over a substrate, and forming an opening within a dielectric protection layer over the ILD layer. A bottom electrode layer is formed within the opening and over the dielectric protection layer. A chemical mechanical planarization (CMP) process is performed on the bottom electrode layer to form a bottom electrode structure having a planar upper surface and a projection that protrudes outward from a lower surface of the bottom electrode structure to within the opening. A memory element is formed over the bottom electrode structure, and a top electrode is formed over the memory element.
-
公开(公告)号：US20150194602A1
公开(公告)日：2015-07-09
申请号：US14196416
申请日：2014-03-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Wen Liao , Wen-Ting Chu , Tong-Chern Ong
IPC: H01L45/00
CPC classification number: H01L45/146 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/1675
Abstract: The present disclosure relates to a resistance random access memory (RRAM) device architecture where a Ti metal capping layer is deposited before the deposition of the HK HfO resistance switching layer. Here, the capping layer is below the HK HfO layer, and hence no damage will occur during the top RRAM electrode etching. The outer sidewalls of the capping layer are substantially aligned with the sidewalls of the HfO layer and hence any damage that may occur during future etching steps will happen at the outer side walls of the capping layer that are positioned away from the oxygen vacancy filament (conductive filament) in the HK HfO layer. Thus the architecture in the present disclosure, improves data retention.
Abstract translation: 本公开涉及在沉积HK HfO电阻切换层之前沉积Ti金属覆盖层的电阻随机存取存储器（RRAM）器件结构。 这里，覆盖层在HK HfO层之下，因此在顶部RRAM电极蚀刻期间不会发生损坏。 覆盖层的外侧壁基本上与HfO层的侧壁对准，因此在将来的蚀刻步骤期间可能发生的任何损坏将发生在封盖层的远离氧空位丝的外侧壁（导电 灯丝）在HK HfO层。 因此，本公开的架构改善了数据保留。
-
公开(公告)号：US11316096B2
公开(公告)日：2022-04-26
申请号：US16899700
申请日：2020-06-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Harry-Hak-Lay Chuang , Hung Cho Wang , Tong-Chern Ong , Wen-Ting Chu , Yu-Wen Liao , Kuei-Hung Shen , Kuo-Yuan Tu , Sheng-Huang Huang
Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.
-
公开(公告)号：US11183631B2
公开(公告)日：2021-11-23
申请号：US16662422
申请日：2019-10-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wen-Ting Chu , Tong-Chern Ong , Ying-Lang Wang
Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a bottom electrode that is disposed over a lower interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A data storage structure is arranged over the bottom electrode and a multi-layer top electrode is disposed over the data storage structure. The multi-layer top electrode includes conductive top electrode layers separated by an oxygen barrier structure that is configured to mitigate movement of oxygen between the conductive top electrode layers. A sidewall spacer is disposed directly over the bottom electrode and has a sidewall that covers outermost sidewalls of the conductive top electrode layers and the oxygen barrier structure.
-
公开(公告)号：US20200303629A1
公开(公告)日：2020-09-24
申请号：US16899700
申请日：2020-06-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Harry-Hak-Lay Chuang , Hung Cho Wang , Tong-Chern Ong , Wen-Ting Chu , Yu-Wen Liao , Kuei-Hung Shen , Kuo-Yuan Tu , Sheng-Huang Huang
Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.
-
-
-
-
-
-
-
-
-
Search Results
26
records
(took 0.018 seconds)
