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公开(公告)号：US20180097173A1
公开(公告)日：2018-04-05
申请号：US15393892
申请日：2016-12-29
发明人： Harry-Hak-Lay Chuang , Hung Cho Wang , Tong-Chern Ong , Wen-Ting Chu , Yu-Wen Liao , Kuei-Hung Shen , Kuo-Yuan Tu , Sheng-Huang Huang
CPC分类号： H01L43/12 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1675
摘要： The present disclosure relates to a method of manufacturing a memory device. The method is performed by forming an inter-layer dielectric (ILD) layer over a substrate, and forming an opening within a dielectric protection layer over the ILD layer. A bottom electrode layer is formed within the opening and over the dielectric protection layer. A chemical mechanical planarization (CMP) process is performed on the bottom electrode layer to form a bottom electrode structure having a planar upper surface and a projection that protrudes outward from a lower surface of the bottom electrode structure to within the opening. A memory element is formed over the bottom electrode structure, and a top electrode is formed over the memory element.
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公开(公告)号：US10164169B2
公开(公告)日：2018-12-25
申请号：US15393892
申请日：2016-12-29
发明人： Harry-Hak-Lay Chuang , Hung Cho Wang , Tong-Chern Ong , Wen-Ting Chu , Yu-Wen Liao , Kuei-Hung Shen , Kuo-Yuan Tu , Sheng-Huang Huang
摘要： The present disclosure relates to a method of manufacturing a memory device. The method is performed by forming an inter-layer dielectric (ILD) layer over a substrate, and forming an opening within a dielectric protection layer over the ILD layer. A bottom electrode layer is formed within the opening and over the dielectric protection layer. A chemical mechanical planarization (CMP) process is performed on the bottom electrode layer to form a bottom electrode structure having a planar upper surface and a projection that protrudes outward from a lower surface of the bottom electrode structure to within the opening. A memory element is formed over the bottom electrode structure, and a top electrode is formed over the memory element.
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公开(公告)号：US11316096B2
公开(公告)日：2022-04-26
申请号：US16899700
申请日：2020-06-12
发明人： Harry-Hak-Lay Chuang , Hung Cho Wang , Tong-Chern Ong , Wen-Ting Chu , Yu-Wen Liao , Kuei-Hung Shen , Kuo-Yuan Tu , Sheng-Huang Huang
摘要： The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.
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公开(公告)号：US20200303629A1
公开(公告)日：2020-09-24
申请号：US16899700
申请日：2020-06-12
发明人： Harry-Hak-Lay Chuang , Hung Cho Wang , Tong-Chern Ong , Wen-Ting Chu , Yu-Wen Liao , Kuei-Hung Shen , Kuo-Yuan Tu , Sheng-Huang Huang
摘要： The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.
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公开(公告)号：US10686125B2
公开(公告)日：2020-06-16
申请号：US16222031
申请日：2018-12-17
发明人： Harry-Hak-Lay Chuang , Hung Cho Wang , Tong-Chern Ong , Wen-Ting Chu , Yu-Wen Liao , Kuei-Hung Shen , Kuo-Yuan Tu , Sheng-Huang Huang
摘要： The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes a dielectric protection layer disposed over a dielectric structure that laterally surrounds one or more conductive interconnect layers. The dielectric protection layer has a protrusion extending outward from an upper surface of the dielectric protection layer. A bottom electrode is disposed over the dielectric protection layer and has sidewalls extending outward from a lower surface of the bottom electrode through the dielectric protection layer. The bottom electrode has a substantially planar upper surface over the protrusion. A data storage element is over the substantially planar upper surface of the bottom electrode, and a top electrode is over the data storage element.
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公开(公告)号：US20190123264A1
公开(公告)日：2019-04-25
申请号：US16222031
申请日：2018-12-17
发明人： Harry-Hak-Lay Chuang , Hung Cho Wang , Tong-Chern Ong , Wen-Ting Chu , Yu-Wen Liao , Kuei-Hung Shen , Kuo-Yuan Tu , Sheng-Huang Huang
CPC分类号： H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L45/1675
摘要： The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes a dielectric protection layer disposed over a dielectric structure that laterally surrounds one or more conductive interconnect layers. The dielectric protection layer has a protrusion extending outward from an upper surface of the dielectric protection layer. A bottom electrode is disposed over the dielectric protection layer and has sidewalls extending outward from a lower surface of the bottom electrode through the dielectric protection layer. The bottom electrode has a substantially planar upper surface over the protrusion. A data storage element is over the substantially planar upper surface of the bottom electrode, and a top electrode is over the data storage element.
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公开(公告)号：US20190066820A1
公开(公告)日：2019-02-28
申请号：US15690303
申请日：2017-08-30
发明人： Chia-Yu Wang , Ching-Huang Wang , Chun-Jung Lin , Tien-Wei Chiang , Meng-Chun Shih , Kuei-Hung Shen
摘要： The disclosure is related a method for testing a magnetic memory device and a test apparatus are provided. In some exemplary embodiments, the method includes at least the following steps. The magnetic memory device is initialized by applying a first magnetic field to force write a first data to the magnetic memory device. Then, a second magnetic field is applied to the magnetic memory device. Second data may be obtained from the magnetic memory device by performing a chip probing process. Accordingly, performance of the magnetic memory device may be determined based on the second data.
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公开(公告)号：US10038137B2
公开(公告)日：2018-07-31
申请号：US15281428
申请日：2016-09-30
CPC分类号： H01L43/08 , H01L27/222 , H01L43/02 , H01L43/12
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a magnetoresistive random access memory (MRAM) device in an insulating layer. The MRAM device includes a first electrode, a magnetic tunnel junction (MTJ) over the first electrode, a second electrode over the MTJ, and an insulating spacer surrounding sidewalls of the first electrode, the MTJ, and the second electrode. Top surfaces of the insulating spacer and the second electrode are exposed from the insulating layer. The semiconductor device structure also includes a conductive pad over the insulating layer and electrically connected to the second electrode. The MTJ is entirely covered by the conductive pad.
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公开(公告)号：US10665321B2
公开(公告)日：2020-05-26
申请号：US15690303
申请日：2017-08-30
发明人： Chia-Yu Wang , Ching-Huang Wang , Chun-Jung Lin , Tien-Wei Chiang , Meng-Chun Shih , Kuei-Hung Shen
IPC分类号： G11C29/00 , G11C29/56 , G11C29/50 , G11C11/16 , H01L27/22 , G11C29/44 , G11C29/04 , G11C29/10
摘要： The disclosure is related a method for testing a magnetic memory device and a test apparatus are provided. In some exemplary embodiments, the method includes at least the following steps. The magnetic memory device is initialized by applying a first magnetic field to force write a first data to the magnetic memory device. Then, a second magnetic field is applied to the magnetic memory device. Second data may be obtained from the magnetic memory device by performing a chip probing process. Accordingly, performance of the magnetic memory device may be determined based on the second data.
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