公开(公告)号：US20190019753A1

公开(公告)日：2019-01-17

申请号：US16124567

申请日：2018-09-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I YANG ,  Tien-I BAO ,  Tien-Lu LIN ,  Wei-Chen CHU

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/48

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer over a first substrate, and the dielectric layer has a plurality of openings. The method also includes forming a first graphene layer in the openings and over the first dielectric layer, and forming an insulating layer in the first graphehe layer. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second graphene layer in and over the second dielectric layer. A portion of the second graphene layer interfaces with a portion of the first graphene layer.

公开(公告)号：US20180164698A1

公开(公告)日：2018-06-14

申请号：US15586881

申请日：2017-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Hsiang-Wei LIU ,  Shau-Lin SHUE ,  Li-Lin SU ,  Yung-Hsu WU

IPC: G03F7/20 ,  H01L21/768 ,  G03F7/004 ,  G03F7/00 ,  G03F7/09

CPC classification number: G03F7/70633 ,  G03F7/0035 ,  G03F7/0043 ,  G03F7/0047 ,  G03F7/094 ,  G03F7/70625 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76849 ,  H01L21/76885 ,  H01L21/76897

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

公开(公告)号：US20170229396A1

公开(公告)日：2017-08-10

申请号：US15016866

申请日：2016-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Tien-I BAO ,  Tien-Lu LIN ,  Wei-Chen CHU

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC classification number: H01L23/5283 ,  H01L21/76877 ,  H01L21/76892 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53276

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and an interconnect structure formed over the substrate. The interconnect structure includes a first dielectric layer formed over the substrate, and a first graphene layer formed in and on the first dielectric layer. The first graphene layer includes a first portion in the first dielectric layer and a second portion on the first dielectric layer and a first insulating layer formed over the first portion of the first graphene layer.