公开(公告)号：US20170092591A1

公开(公告)日：2017-03-30

申请号：US15361699

申请日：2016-11-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Kang FU ,  Hsien-Chang WU ,  Li-Lin SU ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/532 ,  H01L21/321 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L23/53238 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266

Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.

公开(公告)号：US20190067089A1

公开(公告)日：2019-02-28

申请号：US15691035

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Li-Lin SU ,  Shin-Yi YANG ,  Cheng-Chi CHUANG ,  Hsin-Ping CHEN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a conductive feature in a first dielectric layer. The semiconductor device structure also includes an etching stop layer over the first dielectric layer and a second dielectric layer over the etching stop layer. The semiconductor device structure further includes a conductive via in the etching stop layer and the second dielectric layer. In addition, the semiconductor device structure includes a conductive line over the conductive via. The semiconductor device structure also includes a first barrier liner covering the bottom surface of the conductive line. The semiconductor device structure further includes a second barrier liner surrounding sidewalls of the conductive line and the conductive via. The conductive line and the conductive via are confined in the first barrier liner and the second barrier liner.

公开(公告)号：US20180164698A1

公开(公告)日：2018-06-14

申请号：US15586881

申请日：2017-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Hsiang-Wei LIU ,  Shau-Lin SHUE ,  Li-Lin SU ,  Yung-Hsu WU

IPC: G03F7/20 ,  H01L21/768 ,  G03F7/004 ,  G03F7/00 ,  G03F7/09

CPC classification number: G03F7/70633 ,  G03F7/0035 ,  G03F7/0043 ,  G03F7/0047 ,  G03F7/094 ,  G03F7/70625 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76849 ,  H01L21/76885 ,  H01L21/76897

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

公开(公告)号：US20170287842A1

公开(公告)日：2017-10-05

申请号：US15632184

申请日：2017-06-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Kang FU ,  Hsien-Chang WU ,  Li-Lin SU ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/532 ,  H01L21/321 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L23/53238 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266

Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.