公开(公告)号：US20180151416A1

公开(公告)日：2018-05-31

申请号：US15389060

申请日：2016-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Tien WU ,  Hsiang-Wei LIU ,  Tai-I YANG ,  Wei-Chen CHU

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76816 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528

Abstract: Two-dimensional (2-D) interconnects in a one-dimensional (1-D) patterning layout for integrated circuits is disclosed. This disclosure provides methods of connecting even or odd numbered lines that are in the x-direction of a 1-D patterning layout through 2-D interconnects in the y-direction. Depending on device design needs, 2-D interconnects may be perpendicular or non-perpendicular to the even or odd numbered lines. The freedom of two-dimensional patterning compared to conventional self-aligned multiple patterning (SAMP) processes used in the 1-D patterning processes is provided. The two-dimensional patterning described herein provides line widths that match the critical dimensions in both x and y directions. The separation between the 1-D lines or between 2-D interconnects and the end of 1-D lines can be kept to a constant and at a minimum.

公开(公告)号：US20210035853A1

公开(公告)日：2021-02-04

申请号：US17065253

申请日：2020-10-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Hsin-Ping CHEN ,  Chih-Wei LU ,  Chung-Ju LEE

IPC: H01L21/768 ,  H01L23/528

Abstract: A semiconductor structure includes an integrated circuit, a first dielectric layer over the integrated circuit, an etch stop layer over the first dielectric layer, a barrier layer over the etch stop layer, a conductive layer over the barrier layer, and a void region vertically extending through the conductive layer, the barrier layer, and the etch stop layer. The void region has an upper portion, a middle portion below the upper portion, and a lower portion below the middle portion, the middle portion. The middle portion is narrower than the upper portion and the lower portion.

公开(公告)号：US20190326157A1

公开(公告)日：2019-10-24

申请号：US16458399

申请日：2019-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Hsin-Ping CHEN ,  Chih-Wei LU ,  Chung-Ju LEE

IPC: H01L21/768 ,  H01L23/528

Abstract: A semiconductor structure includes an integrated circuit, a first dielectric layer, an etching stop layer, a barrier layer, a conductive layer, and a second dielectric layer. The first dielectric layer is over the integrated circuit. The etching stop layer is over the first dielectric layer. The barrier layer has an upper portion extending along a top surface of the etching stop layer and a lower portion extending downwardly from the upper portion along a sidewall of the etching stop layer and a sidewall of the first dielectric layer. The conductive layer is over the barrier layer and having a void region extending through the conductive layer, the barrier layer and the etching stop layer. The second dielectric layer is over the conductive layer and the void region.

公开(公告)号：US20190043730A1

公开(公告)日：2019-02-07

申请号：US15668216

申请日：2017-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei LIU ,  Chia-Tien WU ,  Wei-Chen CHU

IPC: H01L21/3105 ,  H01L21/48 ,  H01L21/308 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/033

Abstract: A method for forming a semiconductor device structure includes forming a first dielectric layer over a semiconductor substrate and forming an etch stop layer with a hole over the first dielectric layer. The method also includes forming a second dielectric layer over the etch stop layer and forming a first mask element with a trench opening over the second dielectric layer. The method further includes forming a second mask element over the first mask element, and the second mask element has a via opening. In addition, the method includes etching the second dielectric layer through the via opening and etching the second dielectric layer through the trench opening. As a result, a trench and a via hole are formed in the second dielectric layer and the first dielectric layer, respectively. The method includes forming a conductive material in the via hole and the trench.

公开(公告)号：US20190067187A1

公开(公告)日：2019-02-28

申请号：US15689784

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Yung-Hsu WU ,  Chung-Ju LEE

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive line over the semiconductor substrate. The semiconductor device structure also includes a conductive via on the conductive line. The conductive via has an upper portion and a protruding portion. The protruding portion extends from a bottom of the upper portion towards the conductive line. The bottom of the upper portion is wider than a top of the upper portion. The semiconductor device structure further includes a dielectric layer over the semiconductor substrate, and the dielectric layer surrounds the conductive line and the conductive via.

公开(公告)号：US20190027406A1

公开(公告)日：2019-01-24

申请号：US15652901

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chen CHU ,  Hsiang-Wei LIU ,  Tai-I YANG ,  Chia-Tien WU

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76885 ,  H01L21/76852 ,  H01L21/76864 ,  H01L23/5226

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first conductive feature in a first dielectric layer and a second conductive feature over the first dielectric layer. The semiconductor device structure also includes a conductive via between the first conductive feature and the second conductive feature. The conductive via includes an etching stop layer over the first conductive feature, a conductive pillar over the etching stop layer, and a capping layer surrounding the conductive pillar and the etching stop layer. The first conductive feature and the second conductive feature are electrically connected to each other through the capping layer, the conductive pillar, and the etching stop layer. The semiconductor device structure further includes a second dielectric layer over the first dielectric layer and below the second conductive feature. The second dielectric layer surrounds the conductive via.

公开(公告)号：US20180166330A1

公开(公告)日：2018-06-14

申请号：US15498259

申请日：2017-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chen CHU ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Chia-Tien Wu

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53276

Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

公开(公告)号：US20200343180A1

公开(公告)日：2020-10-29

申请号：US16926942

申请日：2020-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Yung-Hsu WU ,  Chung-Ju LEE

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a conductive layer over a semiconductor substrate and forming a sacrificial layer over the conductive layer. The method also includes partially removing the sacrificial layer to form a first dummy element. The method further includes etching the conductive layer with the first dummy element as an etching mask to form a conductive line. In addition, the method includes partially removing the first dummy element to form a second dummy element over the conductive line. The method also includes forming a dielectric layer to surround the conductive line and the second dummy element and removing the second dummy element to form a via hole exposing the conductive line. The method further includes forming a conductive via in the via hole.

公开(公告)号：US20180308749A1

公开(公告)日：2018-10-25

申请号：US16010007

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Cheng-Chi CHUANG ,  Chia-Tien WU ,  Wei-Chen CHU

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813

Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

公开(公告)号：US20190067089A1

公开(公告)日：2019-02-28

申请号：US15691035

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Li-Lin SU ,  Shin-Yi YANG ,  Cheng-Chi CHUANG ,  Hsin-Ping CHEN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a conductive feature in a first dielectric layer. The semiconductor device structure also includes an etching stop layer over the first dielectric layer and a second dielectric layer over the etching stop layer. The semiconductor device structure further includes a conductive via in the etching stop layer and the second dielectric layer. In addition, the semiconductor device structure includes a conductive line over the conductive via. The semiconductor device structure also includes a first barrier liner covering the bottom surface of the conductive line. The semiconductor device structure further includes a second barrier liner surrounding sidewalls of the conductive line and the conductive via. The conductive line and the conductive via are confined in the first barrier liner and the second barrier liner.