公开(公告)号：US20240104285A1

公开(公告)日：2024-03-28

申请号：US18526337

申请日：2023-12-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC NANJING COMPANY LIMITED

Inventor： Yi-Lin CHUANG ,  Shi-Wen TAN ,  Song LIU ,  Shih-Yao LIN ,  Wen-Yuan FANG

IPC: G06F30/392 ,  G06F30/373 ,  G06F30/394 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/373 ,  G06F30/394 ,  G06F30/398

Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.

公开(公告)号：US20230385520A1

公开(公告)日：2023-11-30

申请号：US18446745

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin CHUANG ,  Shih-Yao LIN ,  Szu-ju HUANG ,  Yin-An CHEN ,  Shih Feng HONG

IPC: G06F30/398 ,  G06N20/00 ,  G06F30/392 ,  G06F30/394 ,  G06F30/327

CPC classification number: G06F30/398 ,  G06N20/00 ,  G06F30/392 ,  G06F30/394 ,  G06F30/327

Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

公开(公告)号：US20210133384A1

公开(公告)日：2021-05-06

申请号：US17151189

申请日：2021-01-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Lin CHUANG ,  Huang-Yu CHEN ,  Yun-Han LEE

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/398

Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first via connects the first metal interconnect to the pin, and the at least one first metal interconnect is perpendicular to the pin.

公开(公告)号：US20180268096A1

公开(公告)日：2018-09-20

申请号：US15724663

申请日：2017-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin CHUANG ,  Ching-Fang CHEN ,  Wei-Li CHEN ,  Wei-Pin CHANGCHIEN ,  Yung-Chin HOU ,  Yun-Han LEE

IPC: G06F17/50 ,  G06N99/00

Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs. The EDA of the present disclosure can substitute the one or more electronic architectural models before, during, and/or after designing, simulating, analyzing, and/or verifying of the one or more electronic architectural designs to effectively decrease the time to market (TTM) for the electronic device.