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    MACHINE-LEARNING DESIGN ENABLEMENT PLATFORM
    1.
    发明申请
    MACHINE-LEARNING DESIGN ENABLEMENT PLATFORM 审中-公开

    公开(公告)号：US20180268096A1

    公开(公告)日：2018-09-20

    申请号：US15724663

    申请日：2017-10-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Lin CHUANG ,  Ching-Fang CHEN ,  Wei-Li CHEN ,  Wei-Pin CHANGCHIEN ,  Yung-Chin HOU ,  Yun-Han LEE

    IPC: G06F17/50 ,  G06N99/00

    Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs. The EDA of the present disclosure can substitute the one or more electronic architectural models before, during, and/or after designing, simulating, analyzing, and/or verifying of the one or more electronic architectural designs to effectively decrease the time to market (TTM) for the electronic device.

    SEMICONDUCTOR DEVICE WITH TRENCH ISOLATION
    2.
    发明申请
    SEMICONDUCTOR DEVICE WITH TRENCH ISOLATION 有权
    半导体器件与TRENCH隔离

    公开(公告)号：US20150303265A1

    公开(公告)日：2015-10-22

    申请号：US14755990

    申请日：2015-06-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yu-Hung CHENG ,  Cheng-Ta WU ,  Yeur-Luen TU ,  Chia-Shiung TSAI ,  Ru-Liang LEE ,  Tung-I LIN ,  Wei-Li CHEN

    IPC: H01L29/167 ,  H01L29/06

    CPC classification number: H01L29/167 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/76237 ,  H01L29/0649

    Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer.

    Abstract translation: 半导体器件包括半导体衬底和沟槽隔离。 沟槽隔离位于半导体衬底中，并且包括外延层和电介质材料。 外延层位于半导体的沟槽中并由其周边封闭，其中通过进行蚀刻和外延工艺形成外延层。 蚀刻和外延工艺包括蚀刻沟槽的侧壁的一部分和沟槽的底表面的一部分，并且形成与侧壁的剩余部分和底表面的剩余部分共形的外延层。 电介质材料由外延层周边封闭。

    Machine-Learning Design Enablement Platform
    4.
    发明申请
    Machine-Learning Design Enablement Platform 审中-公开

    公开(公告)号：US20200272777A1

    公开(公告)日：2020-08-27

    申请号：US16871841

    申请日：2020-05-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Lin CHUANG ,  Ching-Fang CHEN ,  Wei-Li CHEN ,  Wei-Pin CHANGCHIEN ,  Yung-Chin HOU ,  Yun-Han LEE

    IPC: G06F30/27 ,  G06N20/00 ,  G06F30/30 ,  G06F30/3308 ,  G06F30/337 ,  G06F30/373

    Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs. The EDA of the present disclosure can substitute the one or more electronic architectural models before, during, and/or after designing, simulating, analyzing, and/or verifying of the one or more electronic architectural designs to effectively decrease the time to market (TTM) for the electronic device.

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