公开(公告)号：US10892360B2

公开(公告)日：2021-01-12

申请号：US16173721

申请日：2018-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chou Lin ,  Yi-Cheng Chiu ,  Karthick Murukesan ,  Yi-Min Chen ,  Shiuan-Jeng Lin ,  Wen-Chih Chiang ,  Chen-Chien Chang ,  Chih-Yuan Chan ,  Kuo-Ming Wu ,  Chun-Lin Tsai

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

公开(公告)号：US20200219721A1

公开(公告)日：2020-07-09

申请号：US16818013

申请日：2020-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chen Lu ,  Ming-Chang Hsieh ,  Yi-Min Chen

IPC: H01L21/027 ,  H01L21/768 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522

Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

公开(公告)号：US20200058647A1

公开(公告)日：2020-02-20

申请号：US16662496

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Karthick Murukesan ,  Wen-Chih Chiang ,  Chiu-Hua Chung ,  Chun Lin Tsai ,  Kuo-Ming Wu ,  Shiuan-Jeng Lin ,  Tien Sheng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Yi-Cheng Chiu

IPC: H01L27/07 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/78 ,  H01L21/761

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.

公开(公告)号：US20190006460A1

公开(公告)日：2019-01-03

申请号：US15694341

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Cheng Chiu ,  Wen-Chih Chiang ,  Chun Lin Tsai ,  Kuo-Ming Wu ,  Shiuan-Jeng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Karthick Murukesan

IPC: H01L29/06 ,  H01L29/10 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66

Abstract: The present disclosure relates to a high voltage resistor device that is able to receive high voltages using a small footprint, and an associated method of fabrication. In some embodiments, the high voltage resistor device has a substrate including a first region with a first doping type, and a drift region arranged within the substrate over the first region and having a second doping type. A body region having the first doping type laterally contacts the drift region. A drain region having the second doping type is arranged within the drift region, and an isolation structure is over the substrate between the drain region and the body region. A resistor structure is over the isolation structure and has a high-voltage terminal coupled to the drain region and a low-voltage terminal coupled to a gate structure over the isolation structure.

公开(公告)号：US20180226396A1

公开(公告)日：2018-08-09

申请号：US15942728

申请日：2018-04-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC: H01L27/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L27/0288 ,  H01L21/823475 ,  H01L23/5228 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0692 ,  H01L29/405 ,  H01L29/4175 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.

公开(公告)号：US09941268B2

公开(公告)日：2018-04-10

申请号：US14208791

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC: H01L29/00 ,  H01L27/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L27/0288 ,  H01L21/823475 ,  H01L23/5228 ,  H01L27/0629 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a drain region and a channel region surrounding the drain region. A source region surrounds the channel region such that the channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and has an inner edge proximate to the drain. A resistor structure, which is made up of a curved or polygonal path of resistive material, is arranged over the drain and is coupled to the drain. The resistor structure is perimeterally bounded by the inner edge of the gate electrode.

公开(公告)号：US20150262995A1

公开(公告)日：2015-09-17

申请号：US14208791

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC: H01L27/02 ,  H01L23/522 ,  H01L49/02 ,  H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0288 ,  H01L21/823475 ,  H01L23/5228 ,  H01L27/0629 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a drain region and a channel region surrounding the drain region. A source region surrounds the channel region such that the channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and has an inner edge proximate to the drain. A resistor structure, which is made up of a curved or polygonal path of resistive material, is arranged over the drain and is coupled to the drain. The resistor structure is perimeterally bounded by the inner edge of the gate electrode.

Abstract translation: 一些实施例涉及半导体器件。 半导体器件包括漏极区域和围绕漏极区域的沟道区域。 源极区域围绕沟道区域，使得沟道区域将漏极区域与源极区域分离。 栅极电极布置在沟道区域的上方，并且具有靠近漏极的内边缘。 由电阻材料的弯曲或多边形路径构成的电阻器结构布置在漏极上并且耦合到漏极。 电阻器结构由栅电极的内边缘周边界定。

公开(公告)号：US11081352B2

公开(公告)日：2021-08-03

申请号：US16818056

申请日：2020-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chen Lu ,  Ming-Chang Hsieh ,  Yi-Min Chen

IPC: H01L21/027 ,  H01L21/768 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  H01L25/065 ,  H01L25/07 ,  H01L23/535 ,  G03F7/20 ,  H01L21/8234

Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

公开(公告)号：US20210175227A1

公开(公告)日：2021-06-10

申请号：US17155268

申请日：2021-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC: H01L27/02 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L27/06 ,  H01L29/423 ,  H01L23/522

Abstract: Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.

公开(公告)号：US20200211836A1

公开(公告)日：2020-07-02

申请号：US16818056

申请日：2020-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chen Lu ,  Ming-Chang Hsieh ,  Yi-Min Chen

IPC: H01L21/027 ,  H01L21/768 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522

Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.