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    CELL PLACEMENT SITE OPTIMIZATION
    11.
    发明申请
    CELL PLACEMENT SITE OPTIMIZATION 审中-公开

    公开(公告)号：US20180357351A1

    公开(公告)日：2018-12-13

    申请号：US15882288

    申请日：2018-01-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Hung LIN ,  Chung-Hsing WANG ,  Yuan-Te HOU

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F2217/02

    Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.

    DESIGN RULE CHECKING FOR MULTIPLE PATTERNING TECHNOLOGY
    12.
    发明申请
    DESIGN RULE CHECKING FOR MULTIPLE PATTERNING TECHNOLOGY 审中-公开

    公开(公告)号：US20180239862A1

    公开(公告)日：2018-08-23

    申请号：US15962822

    申请日：2018-04-25

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Meng-Kai HSU ,  Yuan-Te HOU ,  Wen-Hao CHEN

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A method is disclosed that includes: if there is a conflict graph including a sub-graph representing that each spacing between any two of three adjacent patterns of quadruple-patterning (QP) patterns in at least one of two abutting cells is smaller than a threshold spacing, performing operations including: identifying if one of edges that connect the three adjacent patterns of QP patterns to one another is constructed along, and/or in parallel with, a boundary between the two abutting cells; modifying multiple-patterning patterns of a layout of an integrated circuit (IC) to exclude patterns representing the sub-graph; and initiating generation of the IC from the modified multiple-patterning patterns, wherein at least one operation of identifying , modifying, or initiating is performed by at least one processor.

    APPARATUS AND METHOD FOR MITIGATING DYNAMIC IR VOLTAGE DROP AND ELECTROMIGRATION AFFECTS
    13.
    发明申请
    APPARATUS AND METHOD FOR MITIGATING DYNAMIC IR VOLTAGE DROP AND ELECTROMIGRATION AFFECTS 有权
    降低动态红外电压下降和电磁效应的装置和方法

    公开(公告)号：US20140264924A1

    公开(公告)日：2014-09-18

    申请号：US13859797

    申请日：2013-04-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Yeh YU ,  Yuan-Te HOU ,  Chung-Min FU ,  Wen-Hao CHEN ,  Wan-Yu LO

    IPC: H01L23/528 ,  H01L21/768

    CPC classification number: H01L23/5286 ,  H01L21/768 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11881 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of functional cells between the plurality of power rails or between the plurality of ground rails or both, and a jumper connection between the vertically separated power rails or ground rails, the jumper connection within a vertically aligned gap among the plurality of functional cells. A method of mitigating IR drop and electromigration affects in an integrated circuit includes forming a plurality of power rails or ground rails, each of the power rails or ground rails on separate vertical levels of a plane of an integrated circuit layout and connecting with a jumper connection at least two power rails or two ground rails, the jumper connection within a vertically aligned gap among cells of the integrated circuit.

    Abstract translation: 集成电路结构包括用于集成电路的多个电源或接地导轨，在平面上垂直分离的多个电源或接地导轨，多个电源轨之间或多个接地导轨之间或多个接地导轨之间的多个功能单元，或两者之间 以及在垂直分离的电源轨或接地轨之间的跨接连接，多个功能单元之间的垂直对齐的间隙内的跨接连接。 在集成电路中减轻IR滴落和电迁移影响的方法包括在集成电路布局的平面的不同的垂直级上形成多个电源轨或接地轨，每个电源轨或接地轨与跳线连接 至少两个电源轨或两个接地轨，所述跨接线连接在所述集成电路的单元之间的垂直对齐的间隙内。

    LEAKAGE ANALYSIS ON SEMICONDUCTOR DEVICE
    15.
    发明申请
    LEAKAGE ANALYSIS ON SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210264093A1

    公开(公告)日：2021-08-26

    申请号：US17315023

    申请日：2021-05-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Cheng-Hua LIU ,  Yun-Xiang LIN ,  Yuan-Te HOU ,  Chung-Hsing WANG

    IPC: G06F30/398 ,  G06F30/367 ,  G06F30/20 ,  G06F30/39

    Abstract: A system includes a library, a processor and an output interface. The library contains at least one leakage lookup table related to leakage current values for different cell abutment cases of abutted cells in a semiconductor device. The cell abutment cases are associated with terminal types of cell edges of the abutted cells. The processor is configured to perform an analysis to detect boundaries between the abutted cells, identify attributes associated with the terminal types of the cell edges, identify the cell abutment cases based on the attributes, and calculate maximal boundary leakages between the abutted cells based on leakage current values associated with the cell abutment cases and leakage probabilities associated with the cell abutment cases. The output interface is for outputting boundary leakages corresponding to the maximal boundary leakages in the semiconductor device. A method is also disclosed herein.

    BLOCK-LEVEL DESIGN METHOD FOR HETEROGENEOUS PG-STRUCTURE CELLS
    17.
    发明申请
    BLOCK-LEVEL DESIGN METHOD FOR HETEROGENEOUS PG-STRUCTURE CELLS 审中-公开

    公开(公告)号：US20180210993A1

    公开(公告)日：2018-07-26

    申请号：US15723308

    申请日：2017-10-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Hung LIN ,  Yuan-Te HOU ,  Chung-Hsing WANG

    IPC: G06F17/50

    Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes forming a first partition by selecting at least one in-boundary PG cell from the group of PG cells, adding at least one out-boundary PG cell from the group of PG cells into the first partition, forming a second partition by selecting the remaining in-boundary PG cells and the remaining out-boundary PG cells in the group of PG cells, calculating the total area of the in-boundary PG cells in the first partition, calculating the total area of the out-boundary PG cells in the first partition, calculating the total area of the in-boundary PG cells in the second partition, calculating the total area of the out-boundary PG cells in the second partition, and calculating the difference between the total areas of in-boundary PG cells in the first partition and the out-boundary PG cells in the first partition.

    ELECTROMIGRATION RESISTANT STANDARD CELL DEVICE
    20.
    发明申请
    ELECTROMIGRATION RESISTANT STANDARD CELL DEVICE 审中-公开
    电抗标准电池装置

    公开(公告)号：US20150248517A1

    公开(公告)日：2015-09-03

    申请号：US14714394

    申请日：2015-05-18

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Lee-Chung LU ,  Wen-Hao CHEN ,  Yuan-Te HOU ,  Shen-Feng CHEN ,  Meng-Fu YOU

    IPC: G06F17/50 ,  H01L23/528

    CPC classification number: G06F17/5077 ,  G06F17/5036 ,  G06F17/5045 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/82 ,  H01L23/5286 ,  H01L27/10 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.

    Abstract translation: 标准单元半导体集成电路器件设计提供了标准单元半导体器件，其包括消耗更多功率的第一标准单元和用户定义的目标标准单元，或者包括与第一标准单元的操作特性不同的其他操作特性。 使用一个电源轨将标准电池单元路由到地线和电源线，并且使用第一电源轨和第二电源轨将目标电池路由到地线和电源线，以减轻任一电力轨道中的电迁移。 两个电源轨包括上电源轨和下电源轨。 中间导电层可以设置在上部和下部电源轨之间，以通过电池之间的横向互连提供信号路由。

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