公开(公告)号：US12237414B2

公开(公告)日：2025-02-25

申请号：US17314815

申请日：2021-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Wen-Yuan Chen ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

公开(公告)号：US20230387301A1

公开(公告)日：2023-11-30

申请号：US18447483

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Wen-Yuan Chen ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L29/7847 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/66742 ,  H01L21/0259 ,  H01L21/26526 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78696

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

公开(公告)号：US20230155008A1

公开(公告)日：2023-05-18

申请号：US18155392

申请日：2023-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Chia-Ying Su ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L27/0924 ,  H01L21/823431 ,  H01L29/0669 ,  H01L29/7851

Abstract: Embodiments of the present disclosure includes a semiconductor device. The semiconductor device includes first suspended nanostructures vertically stacked over one another and disposed on a substrate, a first gate stack engaging the first suspended nanostructures, a first gate spacer disposed on sidewalls of the first gate stack, second suspended nanostructures vertically stacked over one another and disposed on the substrate, a second gate stack engaging the second suspended nanostructures, and a second gate spacer disposed on sidewalls of the second gate stack. A middle portion of the first suspended nanostructures has a first thickness measured in a direction perpendicular to a top surface of the substrate. A middle portion of the second suspended nanostructures has a second thickness measured in the direction. The second thickness is smaller than the first thickness.

公开(公告)号：US11201243B2

公开(公告)日：2021-12-14

申请号：US16559343

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Han-Yu Lin ,  Chun-Yu Chen ,  Chih-Ching Wang ,  Fang-Wei Lee ,  Tze-Chung Lin ,  Li-Te Lin ,  Gwan-Sin Chang ,  Pinyen Lin

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06

Abstract: The current disclosure describes techniques for forming a gate-all-around device where semiconductor layers are released by etching out the buffer layers that are vertically stacked between semiconductor layers in an alternating manner. The buffer layers stacked at different vertical levels include different material compositions, which bring about different etch rates with respect to an etchant that is used to remove at least partially the buffer layers to release the semiconductor layers.

公开(公告)号：US20210376163A1

公开(公告)日：2021-12-02

申请号：US17206646

申请日：2021-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Zhiqiang Wu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary device includes a channel layer, a first source/drain feature, a second source/drain feature, and a metal gate. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment connects the first horizontal segment and the second horizontal segment. The first horizontal segment and the second horizontal segment extend along a first direction, and the vertical segment extends along a second direction. The vertical segment has a width along the first direction and a thickness along the second direction, and the thickness is greater than the width. The channel layer extends between the first source/drain feature and the second source/drain feature along a third direction. The metal gate wraps channel layer. In some embodiments, the first horizontal segment and the second horizontal segment are nanosheets.

公开(公告)号：US11908919B2

公开(公告)日：2024-02-20

申请号：US17200291

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/66484 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming an S/D space; laterally etching the first semiconductor layers through the S/D space, thereby forming recesses; forming a first insulating layer, in the recesses, on the etched first semiconductor layers; after the first insulating layer is formed, forming a second insulating layer, in the recesses, on the first insulating layer, wherein a dielectric constant of the second insulating layer is less than that of the first insulating layer; and forming an S/D epitaxial layer in the S/D space, wherein the second insulating layer is in contact with the S/D epitaxial layer.

公开(公告)号：US20230327025A1

公开(公告)日：2023-10-12

申请号：US18190754

申请日：2023-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Zhiqiang Wu

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/78696 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/6675 ,  H01L29/78645

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary device includes a channel layer, a first source/drain feature, a second source/drain feature, and a metal gate. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment connects the first horizontal segment and the second horizontal segment. The first horizontal segment and the second horizontal segment extend along a first direction, and the vertical segment extends along a second direction. The vertical segment has a width along the first direction and a thickness along the second direction, and the thickness is greater than the width. The channel layer extends between the first source/drain feature and the second source/drain feature along a third direction. The metal gate wraps channel layer. In some embodiments, the first horizontal segment and the second horizontal segment are nanosheets.

公开(公告)号：US11282943B2

公开(公告)日：2022-03-22

申请号：US16901881

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Chung-I Yang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a fin structure having first semiconductor layers and second semiconductor layers alternately stacked, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region thereby forming an opening exposing at least one second semiconductor layer. The method also includes implanting an etch rate modifying species into the at least one second semiconductor layer though the opening thereby forming an implanted portion of the at least one second semiconductor layer. The method further includes selectively etching the implanted portion of the at least one second semiconductor layer, recessing end portions of the first semiconductor layers exposed in the opening, and forming an S/D epitaxial layer in the opening.

公开(公告)号：US20210343858A1

公开(公告)日：2021-11-04

申请号：US17170263

申请日：2021-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Chia-Ying Su ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234

Abstract: Embodiments of the present disclosure includes a method of forming a semiconductor device. The method includes providing a substrate having a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed over the substrate. The method also includes patterning the first semiconductor layers and the second semiconductor layers to form a first fin and a second fin, removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin, and doping a threshold modifying impurity into the first suspended nanostructures in the first fin. The impurity causes transistors formed with the first fin and second fin have different threshold voltages.

公开(公告)号：US09620500B2

公开(公告)日：2017-04-11

申请号：US15158462

申请日：2016-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Chi Wang ,  Chien-Chih Lee ,  Tien-Wei Chiang ,  Ching-Wei Tsai ,  Chih-Ching Wang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh

IPC: H01L29/66 ,  H01L21/336 ,  H01L27/088 ,  H01L29/78 ,  H01L29/45 ,  H01L29/06 ,  H01L23/528 ,  H01L21/283 ,  H01L21/306 ,  H01L21/768 ,  H01L21/31 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/76897 ,  H01L21/823487 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.