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    Leakage pathway prevention in a memory storage device
    11.
    发明授权
    Leakage pathway prevention in a memory storage device 有权

    公开(公告)号：US11264066B2

    公开(公告)日：2022-03-01

    申请号：US16999867

    申请日：2020-08-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shang-Chi Wu ,  Cheng Hung Lee ,  Chien-Kuo Su ,  Chiting Cheng ,  Yu-Hao Hsu ,  Yangsyu Lin

    IPC: G11C7/22 ,  G11C7/10 ,  G11C7/12

    Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices. This specialized circuitry, also referred to as a write driver, writes the electronic data onto these data lines for storage in the one or more memory cells during the write mode of operation.

    DUAL RAIL DEVICE WITH POWER DETECTOR
    13.
    发明申请
    DUAL RAIL DEVICE WITH POWER DETECTOR 审中-公开

    公开(公告)号：US20200020387A1

    公开(公告)日：2020-01-16

    申请号：US16580675

    申请日：2019-09-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yangsyu Lin ,  Chiting Cheng

    IPC: G11C11/417 ,  H01L27/11 ,  H01L23/528 ,  G11C5/14

    Abstract: A dual rail device includes a first power domain circuit coupled to a first power supply through a first header control switch and a second power domain circuit coupled to a second power supply. The first and second power supplies have different steady-state voltage levels. The first power domain circuit is interfaced to the second power domain circuit. The device also includes a power detector circuit for providing a control signal for the first header control switch responsive to a voltage level of the second power supply.

    Negative bitline boost scheme for SRAM write-assist
    19.
    发明授权
    Negative bitline boost scheme for SRAM write-assist 有权
    SRAM写入辅助负位线提升方案

    公开(公告)号：US09070432B2

    公开(公告)日：2015-06-30

    申请号：US14077263

    申请日：2013-11-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-jer Hsieh ,  Yangsyu Lin ,  Hsiao Wen Lu ,  Chiting Cheng ,  Jonathan Tsung-Yung Chang

    IPC: G11C11/00 ,  G11C7/12 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C7/12

    Abstract: A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element.

    Abstract translation: 一种器件包括耦合在位线电压节点和接地节点之间的晶体管开关和耦合到晶体管开关的栅极节点的升压信号电路，其中升压信号电路响应于写使能信号而提供升压信号。 该装置还包括与第一延迟元件串联的第一延迟元件和第一电容器。 第一电容器具有耦合到位线电压节点的第一端和通过第一延迟元件耦合到栅极节点的第二端。

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