公开(公告)号：US10811085B2

公开(公告)日：2020-10-20

申请号：US16580675

申请日：2019-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yangsyu Lin ,  Chiting Cheng

IPC: G11C11/417 ,  H01L27/11 ,  H01L23/528 ,  G11C5/14

Abstract: A dual rail device includes a first power domain circuit coupled to a first power supply through a first header control switch and a second power domain circuit coupled to a second power supply. The first and second power supplies have different steady-state voltage levels. The first power domain circuit is interfaced to the second power domain circuit. The device also includes a power detector circuit for providing a control signal for the first header control switch responsive to a voltage level of the second power supply.

公开(公告)号：US10281502B2

公开(公告)日：2019-05-07

申请号：US15941535

申请日：2018-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Chen Kuo ,  Chiting Cheng ,  Wei-Jer Hsieh

IPC: G01R19/165 ,  G01R19/04 ,  H03K19/0944 ,  H03K19/00 ,  G01R19/00

Abstract: A voltage selection circuit includes: a power detection circuit configured to compare an output voltage with a first input voltage and a second input voltage, respectively; a latch circuit, coupled to the power detection circuit, and configured to flip respective logic states of a pair of output signals when the output voltage is lower than either the first input voltage or the second input voltage; and a selection circuit, coupled to the latch circuit, and configured to use either the first input voltage or the second input voltage as the output voltage based on the respective logic states of the pair of output signals.

公开(公告)号：US10141045B2

公开(公告)日：2018-11-27

申请号：US15471937

申请日：2017-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chiting Cheng ,  Yangsyu Lin

IPC: G11C11/417 ,  H01L27/11 ,  H01L23/528

Abstract: A dual rail device includes a first power domain circuit coupled to a first power supply through a first header control switch and a second power domain circuit coupled to a second power supply. The first and second power supplies have different steady-state voltage levels. The first power domain circuit is interfaced to the second power domain circuit. The device also includes a power detector circuit for providing a control signal for the first header control switch responsive to a voltage level of the second power supply.

公开(公告)号：US09437281B2

公开(公告)日：2016-09-06

申请号：US14727931

申请日：2015-06-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Jer Hsieh ,  Yangsyu Lin ,  Hsiao Wen Lu ,  Chiting Cheng ,  Jonathan Tsung-Yung Chang

IPC: G11C5/14 ,  G11C11/419 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C7/12

Abstract: A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element.

公开(公告)号：US09305635B2

公开(公告)日：2016-04-05

申请号：US14068003

申请日：2013-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yangsyu Lin ,  Hsiao Wen Lu ,  Chiting Cheng ,  Jonathan Tsung-Yung Chang

IPC: G11C5/06 ,  G11C11/419 ,  G11C7/18

CPC classification number: G11C11/419 ,  G11C7/18

Abstract: A semiconductor memory comprises a plurality of sub banks each including one or more rows of memory bit cells connected to a set of local bit lines, wherein the sub banks share a same set of global bit lines for reading/writing data from/to the memory bit cells of the sub banks. The semiconductor memory chip further comprises a plurality of switch elements for each of the sub banks, wherein each of the switch elements connects the local bit line and the global bit line of a corresponding one of the memory bit cells in the sub bank for data transmission between the local bit line and the global bit line. The semiconductor memory chip further comprises a plurality of bank selection signal lines each connected to the switch elements in a corresponding one of the sub banks, wherein the bank selection signal lines carry a plurality of bank selection signals to select one of the sub banks for data transmission between the local bit lines and the global bit lines.

Abstract translation: 半导体存储器包括多个子存储体，每个子存储体包括连接到一组局部位线的一行或多行存储器位单元，其中子存储体共享用于从/向存储器读/写数据的全局位线集合 子库的位单元。 半导体存储器芯片还包括用于每个子存储体的多个开关元件，其中每个开关元件连接子库中对应的一个存储单元的局部位线和全局位线，用于数据传输 在本地位线和全局位线之间。 半导体存储器芯片还包括多个存储体选择信号线，每条存储体选择信号线连接到相应的一个子存储体中的开关元件，其中存储体选择信号线传送多个存储体选择信号以选择一个子存储体用于数据 局部位线与全局位线之间的传输。

公开(公告)号：US10762934B2

公开(公告)日：2020-09-01

申请号：US16263904

申请日：2019-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Chi Wu ,  Cheng Hung Lee ,  Chien-Kuo Su ,  Chiting Cheng ,  Yu-Hao Hsu ,  Yangsyu Lin

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/12

Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices. This specialized circuitry, also referred to as a write driver, writes the electronic data onto these data lines for storage in the one or more memory cells during the write mode of operation.

公开(公告)号：US20190172523A1

公开(公告)日：2019-06-06

申请号：US16181889

申请日：2018-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yangsyu Lin ,  Chiting Cheng

IPC: G11C11/417 ,  G11C5/14 ,  H01L23/528 ,  H01L27/11

Abstract: A dual rail device includes a first power domain circuit coupled to a first power supply through a first header control switch and a second power domain circuit coupled to a second power supply. The first and second power supplies have different steady-state voltage levels. The first power domain circuit is interfaced to the second power domain circuit. The device also includes a power detector circuit for providing a control signal for the first header control switch responsive to a voltage level of the second power supply.

公开(公告)号：US09659603B2

公开(公告)日：2017-05-23

申请号：US14980287

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hektor Huang ,  Yangsyu Lin ,  Yu-Hao Hsu ,  Chia-En Huang ,  Chiting Cheng ,  Chen-Lin Yang ,  Jung-Ping Yang ,  Cheng Hung Lee

IPC: G11C5/14 ,  H02J4/00

CPC classification number: G11C5/147 ,  H02J4/00

Abstract: A power management circuit for an electronic device sequentially activates and/or deactivates electronic circuits of the electronic device. The power management circuit provides a first group of one or more circuit power management signals to activate and/or deactivate a first electronic circuit from among the electronic circuits. Thereafter, the power management circuit provides a corresponding power management signal from among a second group of the one or more circuit power management signals that corresponds to a portion of the first electronic circuit that has been activated and/or deactivated by the first group of the one or more circuit power management signals to activate and/or deactivate a portion of a second electronic circuit from among the electronic circuits. The power management circuit continues to sequentially provide each of the one or more circuit power management signals in a similar manner until the electronic circuits of the electronic device have been activated and/or deactivated.

公开(公告)号：US09762216B1

公开(公告)日：2017-09-12

申请号：US15065166

申请日：2016-03-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mahmut Sinangil ,  Hsin-Hsin Ko ,  Chiting Cheng ,  Yen-Huei Chen ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

IPC: H03L5/00 ,  H03K3/356 ,  H03K19/0185

CPC classification number: H03K3/356113 ,  H03K19/018521

Abstract: A level shifter circuit is provided that uses a boosting circuit. The boosting circuit is configured to improve the operation of the level shifter circuit when the high voltages of voltage domains across the level shifter circuit are widely separated. A circuit apparatus includes a core level shifter circuit that changes a first voltage of an input signal to a second voltage of an output signal. The circuit apparatus further includes a first boosting circuit that is coupled to the core level shifter circuit and generates a first transient voltage applied to the core level shifter circuit when the input signal transitions from a low value to a high value. The circuit apparatus also includes a second boosting circuit that is coupled to the core level shifter circuit and generates a second transient voltage applied to the core level shifter circuit when the input signal transitions from a high value to a low value.

公开(公告)号：US20170040042A1

公开(公告)日：2017-02-09

申请号：US14980287

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hektor Huang ,  Yangsyu Lin ,  Yu-Hao Hsu ,  Chia-En Huang ,  Chiting Cheng ,  Chen-Lin Yang ,  Jung-Ping Yang ,  Cheng Hung Lee

IPC: G11C5/14 ,  H02J4/00

CPC classification number: G11C5/147 ,  H02J4/00

Abstract: A power management circuit for an electronic device is disclosed that sequentially activates and/or deactivates electronic circuits of the electronic device. The power management circuit provides a first group of one or more circuit power management signals to activate and/or deactivate a first electronic circuit from among the electronic circuits. Thereafter, the power management circuit provides a corresponding power management signal from among a second group of the one or more circuit power management signals that corresponds to a portion of the first electronic circuit that has been activated and/or deactivated by the first group of the one or more circuit power management signals to activate and/or deactivate a portion of a second electronic circuit from among the electronic circuits. The power management circuit continues to sequentially provide each of the one or more circuit power management signals in a similar manner until the electronic circuits of the electronic device have been activated and/or deactivated.

Abstract translation: 公开了一种用于电子设备的电源管理电路，其顺序地激活和/或去激活电子设备的电子电路。 功率管理电路提供第一组一个或多个电路功率管理信号以激活和/或去激活来自电子电路之间的第一电子电路。 此后，电源管理电路从一个或多个电路电源管理信号的第二组中提供相应的功率管理信号，其对应于已经被第一组的第一组激活和/或去激活的第一电子电路的一部分 一个或多个电路功率管理信号，用于激活和/或去激活来自电子电路的第二电子电路的一部分。 功率管理电路以类似的方式继续顺序提供一个或多个电路功率管理信号中的每一个，直到电子设备的电子电路已经被激活和/或去激活为止。