公开(公告)号：US20230318581A1

公开(公告)日：2023-10-05

申请号：US18330492

申请日：2023-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Chen KUO ,  Yangsyu Lin ,  Yu-Hao Hsu ,  Cheng Hung Lee ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

IPC: H03K3/012

CPC classification number: H03K3/012

Abstract: The present disclosure describes an example circuit for selecting a voltage supply. The circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is configured to receive a second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.

公开(公告)号：US10685686B2

公开(公告)日：2020-06-16

申请号：US16582029

申请日：2019-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-An Wu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yu-Hao Hsu

IPC: G11C5/14 ,  H03K17/687 ,  H03K17/22

Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.

公开(公告)号：US20150058664A1

公开(公告)日：2015-02-26

申请号：US13972082

申请日：2013-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-An Wu ,  Jung-Ping Yang ,  Chia-En Huang ,  Cheng Hung Lee

IPC: G06F11/10 ,  G06F11/25

CPC classification number: G06F11/25 ,  G11C29/00 ,  G11C29/808 ,  G11C29/848

Abstract: A memory chip comprises a main memory array having a plurality of memory columns, a redundancy memory column associated with the main memory array, and a hit logic circuitry configured to generate a plurality of hit logic signals by a plurality of hit logic units in the hit logic circuitry to enable dynamic replacement of a defective memory cell in one of the memory columns for dynamic replacement by the redundancy memory column when the memory array is in operation.

Abstract translation: 存储器芯片包括具有多个存储器列的主存储器阵列，与主存储器阵列相关联的冗余存储器列，以及命中逻辑电路，其被配置为通过命中中的多个命中逻辑单元产生多个命中逻辑信号 逻辑电路，用于在存储器列之一中动态替换存储器列之一中的有缺陷的存储器单元，以便在存储器阵列运行时由冗余存储器列进行动态替换。

公开(公告)号：US20140266436A1

公开(公告)日：2014-09-18

申请号：US13888620

申请日：2013-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng Hung Lee ,  Hektor Huang ,  Chi-Kai Hsieh ,  Shi-Wei Chang ,  Hong-Chen Cheng

IPC: H03F3/45

CPC classification number: H03F3/45076 ,  G11C7/02 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1048

Abstract: The present disclosure relates to a differential sense amplifier comprising first and second cross-coupled inverters with first and second complimentary storage nodes. A first current control element changes a current through the first cross-coupled inverter based upon an output of a second cross-coupled inverter, and a second current control element changes a current through the second cross-coupled inverter based upon an output of the first cross-coupled inverter. Other devices and methods are also disclosed.

Abstract translation: 本公开涉及一种差分读出放大器，包括具有第一和第二互补存储节点的第一和第二交叉耦合的反相器。 第一电流控制元件基于第二交叉耦合逆变器的输出改变通过第一交叉耦合逆变器的电流，并且第二电流控制元件基于第一交流耦合逆变器的输出改变通过第二交叉耦合逆变器的电流 交叉耦合逆变器。 还公开了其它装置和方法。

公开(公告)号：US20230389255A1

公开(公告)日：2023-11-30

申请号：US18446546

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Sheng WANG ,  Yangsyu Lin ,  Cheng Hung Lee

IPC: H10B10/00 ,  G11C11/419 ,  G11C11/412

CPC classification number: H10B10/12 ,  G11C11/419 ,  G11C11/412 ,  H10B10/18

Abstract: The present disclosure describes embodiments of a memory device with a pre-charge circuit. The memory device can include a memory cell, and the pre-charge circuit can include a first transistor and a second transistor. The first transistor includes a first gate terminal, a first source/drain (S/D) terminal coupled to a reference voltage, and a second S/D terminal coupled to a first terminal of the memory cell. The second transistor includes a second gate terminal, a third S/D terminal coupled to the reference voltage, and a fourth S/D terminal coupled to the second terminal of the memory cell. The first and second transistors are configured to pass the reference voltage in response to the control signal being applied to the first and second gate terminals, respectively.

公开(公告)号：US11264066B2

公开(公告)日：2022-03-01

申请号：US16999867

申请日：2020-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Chi Wu ,  Cheng Hung Lee ,  Chien-Kuo Su ,  Chiting Cheng ,  Yu-Hao Hsu ,  Yangsyu Lin

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/12

Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices. This specialized circuitry, also referred to as a write driver, writes the electronic data onto these data lines for storage in the one or more memory cells during the write mode of operation.

公开(公告)号：US10666438B2

公开(公告)日：2020-05-26

申请号：US16160397

申请日：2018-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Che Tsai ,  Cheng Hung Lee ,  Shih-Lien Linus Lu ,  Yi-Ju Chen

IPC: H04L9/32 ,  G11C7/08 ,  G11C7/12 ,  G06F21/73

Abstract: A memory storage device is fabricated using a semiconductor fabrication process. Often times, manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process can cause the memory storage device to differ from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process. For example, uncontrollable random physical processes in the semiconductor fabrication process can cause small differences, such as differences in doping concentrations, oxide thicknesses, channel lengths, structural widths, and/or parasitics to provide some examples, between these memory storage devices. These small differences can cause bitlines within the memory storage device to be physically unique with no two bitlines being identical. As a result, the uncontrollable random physical processes in the semiconductor fabrication process can cause electronic data read from the memory storage device to propagate along the bitlines at different rates. This physical uniqueness of the bitlines can be utilized to implement a physical unclonable function (PUF) allowing the memory storage device to be differentiated from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process.

公开(公告)号：US20190004718A1

公开(公告)日：2019-01-03

申请号：US15938502

申请日：2018-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hao HSU ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Chiting Cheng ,  Fu-An Wu ,  Hung-Jen Liao ,  Jung-Ping Yang ,  Jonathan Tsung-Yung Chang ,  Wei Min Chan ,  Yen-Huei Chen ,  Yangsyu Lin ,  Chien-Chen Lin

IPC: G06F3/06 ,  G11C11/4074 ,  G11C16/12 ,  G11C16/30 ,  G11C5/14

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to control minimize power consumption.

公开(公告)号：US09281031B2

公开(公告)日：2016-03-08

申请号：US14603393

申请日：2015-01-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jonathan Tsung-Yung Chang ,  Cheng Hung Lee ,  Chung-Cheng Chou ,  Hung-Jen Liao ,  Bin-Hau Lo

IPC: G11C17/00 ,  G11C7/12 ,  G11C7/06 ,  G11C11/419 ,  G11C11/412

CPC classification number: G11C7/12 ,  G11C7/067 ,  G11C11/412 ,  G11C11/419

Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.

公开(公告)号：US10972292B2

公开(公告)日：2021-04-06

申请号：US16383383

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Che Tsai ,  Shih-Lien Linus Lu ,  Cheng Hung Lee ,  Chia-En Huang

IPC: H04L9/32 ,  G11C7/06 ,  G11C11/4091 ,  H04L9/08

Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.