公开(公告)号：US10685686B2

公开(公告)日：2020-06-16

申请号：US16582029

申请日：2019-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-An Wu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yu-Hao Hsu

IPC: G11C5/14 ,  H03K17/687 ,  H03K17/22

Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.

公开(公告)号：US20150058664A1

公开(公告)日：2015-02-26

申请号：US13972082

申请日：2013-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-An Wu ,  Jung-Ping Yang ,  Chia-En Huang ,  Cheng Hung Lee

IPC: G06F11/10 ,  G06F11/25

CPC classification number: G06F11/25 ,  G11C29/00 ,  G11C29/808 ,  G11C29/848

Abstract: A memory chip comprises a main memory array having a plurality of memory columns, a redundancy memory column associated with the main memory array, and a hit logic circuitry configured to generate a plurality of hit logic signals by a plurality of hit logic units in the hit logic circuitry to enable dynamic replacement of a defective memory cell in one of the memory columns for dynamic replacement by the redundancy memory column when the memory array is in operation.

Abstract translation: 存储器芯片包括具有多个存储器列的主存储器阵列，与主存储器阵列相关联的冗余存储器列，以及命中逻辑电路，其被配置为通过命中中的多个命中逻辑单元产生多个命中逻辑信号 逻辑电路，用于在存储器列之一中动态替换存储器列之一中的有缺陷的存储器单元，以便在存储器阵列运行时由冗余存储器列进行动态替换。

公开(公告)号：US11675505B2

公开(公告)日：2023-06-13

申请号：US17717491

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hao Hsu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Chiting Cheng ,  Fu-An Wu ,  Hung-Jen Liao ,  Jung-Ping Yang ,  Jonathan Tsung-Yung Chang ,  Wei Min Chan ,  Yen-Huei Chen ,  Yangsyu Lin ,  Chien-Chen Lin

IPC: G06F3/06 ,  G11C5/14 ,  G11C11/4074 ,  G11C16/12 ,  G11C16/30 ,  H04B10/03 ,  H04B10/27 ,  H04J14/02

CPC classification number: G06F3/0625 ,  G06F3/0679 ,  G11C5/147 ,  G11C11/4074 ,  G11C16/12 ,  G11C16/30 ,  H04B10/03 ,  H04B10/27 ,  H04J14/0228 ,  H04J14/0268

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.

公开(公告)号：US11600626B2

公开(公告)日：2023-03-07

申请号：US16713967

申请日：2019-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Yao-Jen Yang ,  Yih Wang ,  Fu-An Wu

IPC: H01L27/112 ,  G11C7/10 ,  H01L23/522 ,  G11C17/16 ,  H01L23/525 ,  G11C5/06 ,  G11C8/08 ,  G11C17/18

Abstract: A structure includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

公开(公告)号：US11301148B2

公开(公告)日：2022-04-12

申请号：US17201931

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hao Hsu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Chiting Cheng ,  Fu-An Wu ,  Hung-Jen Liao ,  Jung-Ping Yang ,  Jonathan Tsung-Yung Chang ,  Wei Min Chan ,  Yen-Huei Chen ,  Yangsyu Lin ,  Chien-Chen Lin

IPC: G11C5/14 ,  G06F3/06 ,  G11C11/4074 ,  G11C16/30 ,  G11C16/12 ,  H04B10/03 ,  H04B10/27 ,  H04J14/02

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.

公开(公告)号：US10949100B2

公开(公告)日：2021-03-16

申请号：US16685722

申请日：2019-11-15

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Yu-Hao Hsu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Chiting Cheng ,  Fu-An Wu ,  Hung-Jen Liao ,  Jung-Ping Yang ,  Jonathan Tsung-Yung Chang ,  Wei Min Chan ,  Yen-Huei Chen ,  Yangsyu Lin ,  Chien-Chen Lin

IPC: G11C5/14 ,  G06F3/06 ,  G11C11/4074 ,  G11C16/30 ,  G11C16/12 ,  H04B10/03 ,  H04B10/27 ,  H04J14/02

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.

公开(公告)号：US20200020363A1

公开(公告)日：2020-01-16

申请号：US16582029

申请日：2019-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-An Wu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yu-Hao Hsu

IPC: G11C5/14 ,  H03K17/22 ,  H03K17/687

Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.

公开(公告)号：US20190005990A1

公开(公告)日：2019-01-03

申请号：US15902118

申请日：2018-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-An Wu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yu-Hao Hsu

IPC: G11C5/14 ,  H03K17/687

Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.

公开(公告)号：US12230359B2

公开(公告)日：2025-02-18

申请号：US18164282

申请日：2023-02-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Yao-Jen Yang ,  Yih Wang ,  Fu-An Wu

IPC: G11C7/10 ,  G11C5/06 ,  G11C8/08 ,  G11C17/16 ,  G11C17/18 ,  H01L23/522 ,  H01L23/525 ,  H10B20/25

Abstract: A semiconductor device includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

公开(公告)号：US20190004718A1

公开(公告)日：2019-01-03

申请号：US15938502

申请日：2018-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hao HSU ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Chiting Cheng ,  Fu-An Wu ,  Hung-Jen Liao ,  Jung-Ping Yang ,  Jonathan Tsung-Yung Chang ,  Wei Min Chan ,  Yen-Huei Chen ,  Yangsyu Lin ,  Chien-Chen Lin

IPC: G06F3/06 ,  G11C11/4074 ,  G11C16/12 ,  G11C16/30 ,  G11C5/14

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to control minimize power consumption.