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公开(公告)号：US20170040042A1
公开(公告)日：2017-02-09
申请号：US14980287
申请日：2015-12-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hektor Huang , Yangsyu Lin , Yu-Hao Hsu , Chia-En Huang , Chiting Cheng , Chen-Lin Yang , Jung-Ping Yang , Cheng Hung Lee
Abstract: A power management circuit for an electronic device is disclosed that sequentially activates and/or deactivates electronic circuits of the electronic device. The power management circuit provides a first group of one or more circuit power management signals to activate and/or deactivate a first electronic circuit from among the electronic circuits. Thereafter, the power management circuit provides a corresponding power management signal from among a second group of the one or more circuit power management signals that corresponds to a portion of the first electronic circuit that has been activated and/or deactivated by the first group of the one or more circuit power management signals to activate and/or deactivate a portion of a second electronic circuit from among the electronic circuits. The power management circuit continues to sequentially provide each of the one or more circuit power management signals in a similar manner until the electronic circuits of the electronic device have been activated and/or deactivated.
Abstract translation: 公开了一种用于电子设备的电源管理电路，其顺序地激活和/或去激活电子设备的电子电路。 功率管理电路提供第一组一个或多个电路功率管理信号以激活和/或去激活来自电子电路之间的第一电子电路。 此后，电源管理电路从一个或多个电路电源管理信号的第二组中提供相应的功率管理信号，其对应于已经被第一组的第一组激活和/或去激活的第一电子电路的一部分 一个或多个电路功率管理信号，用于激活和/或去激活来自电子电路的第二电子电路的一部分。 功率管理电路以类似的方式继续顺序提供一个或多个电路功率管理信号中的每一个，直到电子设备的电子电路已经被激活和/或去激活为止。
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公开(公告)号：US09218262B2
公开(公告)日：2015-12-22
申请号：US13972082
申请日：2013-08-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fu-An Wu , Jung-Ping Yang , Chia-En Huang , Cheng Hung Lee
CPC classification number: G06F11/25 , G11C29/00 , G11C29/808 , G11C29/848
Abstract: A memory chip comprises a main memory array having a plurality of memory columns, a redundancy memory column associated with the main memory array, and a hit logic circuitry configured to generate a plurality of hit logic signals by a plurality of hit logic units in the hit logic circuitry to enable dynamic replacement of a defective memory cell in one of the memory columns for dynamic replacement by the redundancy memory column when the memory array is in operation.
Abstract translation: 存储器芯片包括具有多个存储器列的主存储器阵列，与主存储器阵列相关联的冗余存储器列，以及命中逻辑电路，其被配置为通过命中中的多个命中逻辑单元产生多个命中逻辑信号 逻辑电路，用于在存储器列之一中动态替换存储器列之一中的有缺陷的存储器单元，以便在存储器阵列运行时由冗余存储器列进行动态替换。
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公开(公告)号：US09659603B2
公开(公告)日：2017-05-23
申请号：US14980287
申请日：2015-12-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hektor Huang , Yangsyu Lin , Yu-Hao Hsu , Chia-En Huang , Chiting Cheng , Chen-Lin Yang , Jung-Ping Yang , Cheng Hung Lee
Abstract: A power management circuit for an electronic device sequentially activates and/or deactivates electronic circuits of the electronic device. The power management circuit provides a first group of one or more circuit power management signals to activate and/or deactivate a first electronic circuit from among the electronic circuits. Thereafter, the power management circuit provides a corresponding power management signal from among a second group of the one or more circuit power management signals that corresponds to a portion of the first electronic circuit that has been activated and/or deactivated by the first group of the one or more circuit power management signals to activate and/or deactivate a portion of a second electronic circuit from among the electronic circuits. The power management circuit continues to sequentially provide each of the one or more circuit power management signals in a similar manner until the electronic circuits of the electronic device have been activated and/or deactivated.
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Patent Agency Ranking
公开(公告)号：US11675505B2
公开(公告)日：2023-06-13
申请号：US17717491
申请日：2022-04-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Hao Hsu , Cheng Hung Lee , Chen-Lin Yang , Chiting Cheng , Fu-An Wu , Hung-Jen Liao , Jung-Ping Yang , Jonathan Tsung-Yung Chang , Wei Min Chan , Yen-Huei Chen , Yangsyu Lin , Chien-Chen Lin
CPC classification number: G06F3/0625 , G06F3/0679 , G11C5/147 , G11C11/4074 , G11C16/12 , G11C16/30 , H04B10/03 , H04B10/27 , H04J14/0228 , H04J14/0268
Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.
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公开(公告)号：US11301148B2
公开(公告)日：2022-04-12
申请号：US17201931
申请日：2021-03-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Hao Hsu , Cheng Hung Lee , Chen-Lin Yang , Chiting Cheng , Fu-An Wu , Hung-Jen Liao , Jung-Ping Yang , Jonathan Tsung-Yung Chang , Wei Min Chan , Yen-Huei Chen , Yangsyu Lin , Chien-Chen Lin
Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.
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公开(公告)号：US10949100B2
公开(公告)日：2021-03-16
申请号：US16685722
申请日：2019-11-15
Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
Inventor： Yu-Hao Hsu , Cheng Hung Lee , Chen-Lin Yang , Chiting Cheng , Fu-An Wu , Hung-Jen Liao , Jung-Ping Yang , Jonathan Tsung-Yung Chang , Wei Min Chan , Yen-Huei Chen , Yangsyu Lin , Chien-Chen Lin
Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.
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公开(公告)号：US20150058664A1
公开(公告)日：2015-02-26
申请号：US13972082
申请日：2013-08-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fu-An Wu , Jung-Ping Yang , Chia-En Huang , Cheng Hung Lee
CPC classification number: G06F11/25 , G11C29/00 , G11C29/808 , G11C29/848
Abstract: A memory chip comprises a main memory array having a plurality of memory columns, a redundancy memory column associated with the main memory array, and a hit logic circuitry configured to generate a plurality of hit logic signals by a plurality of hit logic units in the hit logic circuitry to enable dynamic replacement of a defective memory cell in one of the memory columns for dynamic replacement by the redundancy memory column when the memory array is in operation.
Abstract translation: 存储器芯片包括具有多个存储器列的主存储器阵列，与主存储器阵列相关联的冗余存储器列，以及命中逻辑电路，其被配置为通过命中中的多个命中逻辑单元产生多个命中逻辑信号 逻辑电路，用于在存储器列之一中动态替换存储器列之一中的有缺陷的存储器单元，以便在存储器阵列运行时由冗余存储器列进行动态替换。
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公开(公告)号：US20190004718A1
公开(公告)日：2019-01-03
申请号：US15938502
申请日：2018-03-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Hao HSU , Cheng Hung Lee , Chen-Lin Yang , Chiting Cheng , Fu-An Wu , Hung-Jen Liao , Jung-Ping Yang , Jonathan Tsung-Yung Chang , Wei Min Chan , Yen-Huei Chen , Yangsyu Lin , Chien-Chen Lin
IPC: G06F3/06 , G11C11/4074 , G11C16/12 , G11C16/30 , G11C5/14
Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to control minimize power consumption.
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