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公开(公告)号：US20230237238A1
公开(公告)日：2023-07-27
申请号：US18295085
申请日：2023-04-03
发明人： Shin-Chi Chen , King-Ho Tam , Yu-Ze Lin , Huang-Yu Chen
IPC分类号： G06F30/392 , G06F30/327 , G06F30/31
CPC分类号： G06F30/392 , G06F30/327 , G06F30/31 , G06F2119/18
摘要： A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device, subject to a limiting condition, such as one determined using a cost function. A computer system including one or more EDAs configured to perform the method is also disclosed.
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公开(公告)号：US20220382946A1
公开(公告)日：2022-12-01
申请号：US17331825
申请日：2021-05-27
发明人： Shin-Chi Chen , King-Ho Tam , Yu-Ze Lin , Huang-Yu Chen
IPC分类号： G06F30/392 , G06F30/31 , G06F30/327
摘要： A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device. A computer system including one or more EDAs configured to perform the method is also disclosed.
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公开(公告)号：US11200364B2
公开(公告)日：2021-12-14
申请号：US16583218
申请日：2019-09-25
发明人： Chia Cheng Chen , Ching-Fang Chen , Huang-Yu Chen , Jen Ping Hsu
IPC分类号： G06F9/455 , G06F30/398
摘要： A method, includes: extracting a design data using a computer, wherein the design data includes a net name and a connective layer name of each layout design in each cell; generating a layout pattern corresponding to the design data by assigning an ID to said each layout design, wherein the ID includes a first indicator indicative of the net name and a second indicator indicative of the connective layer name; and checking the layout pattern to locate an error of the layout pattern.
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公开(公告)号：US09292645B2
公开(公告)日：2016-03-22
申请号：US14552095
申请日：2014-11-24
发明人： Huang-Yu Chen , Yuan-Te Hou , Yu-Hsiang Kao , Ken-Hsien Hsieh , Ru-Gun Liu , Lee-Chung Lu
CPC分类号： G06F17/5068 , G03F7/0035 , G06F17/5072 , G06F2217/08 , G06F2217/12
摘要： A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.
摘要翻译： 布置目标图案的方法包括：将目标图案的第一特征的末端分配给保留区域，以及定位其他特征，使得目标图案的其它特征的末端在所述保留区域内没有结束 出区。 目标图案应形成相应的主要特征和切割图案。
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公开(公告)号：US20220382958A1
公开(公告)日：2022-12-01
申请号：US17331693
申请日：2021-05-27
IPC分类号： G06F30/3947
摘要： The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.
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公开(公告)号：US11501052B1
公开(公告)日：2022-11-15
申请号：US17331693
申请日：2021-05-27
IPC分类号： G06F30/00 , G06F30/3947 , G06F30/39
摘要： The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.
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公开(公告)号：US09747402B2
公开(公告)日：2017-08-29
申请号：US14564934
申请日：2014-12-09
发明人： Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
IPC分类号： H01L27/02 , G06F17/50 , H01L23/528 , H01L27/118
CPC分类号： G06F17/5072 , H01L23/5286 , H01L27/0207 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
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公开(公告)号：US09418196B2
公开(公告)日：2016-08-16
申请号：US14598773
申请日：2015-01-16
发明人： Huang-Yu Chen , Yuan-Te Hou , Yu-Hsiang Kao , Ken-Hsien Hsieh , Ru-Gun Liu , Lee-Chung Lu
CPC分类号： G06F17/5081 , G03F7/0035 , G06F17/5068 , G06F17/5072 , G06F2217/08 , G06F2217/12 , Y02P90/265
摘要： A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.
摘要翻译： 一种方法包括用计算系统接收由主图案，第一切割图案和第二切割图案定义的目标图案，检查目标图案是否符合第一约束条件，与第一切割相关联的第一约束 模式，与所述计算系统一起，检查所述目标模式是否符合第二约束，所述第二约束与所述第二剪切模式相关联，并且与所述计算系统一起修改所述模式以响应于确定违反所述第一约束或 在检查期间发现第二个约束。
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19.发明授权公开(公告)号：US08898608B1
公开(公告)日：2014-11-25
申请号：US13942177
申请日：2013-07-15
发明人： Yi-Lin Chuang , Huang-Yu Chen , Yun-Han Lee
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/5068 , G06F17/5072 , G06F2217/06 , G06F2217/84
摘要： A method includes (a) generating timing information of an integrated circuit (IC) floorplan by a processing unit, (b) displaying on a display device a representation of the IC floorplan according to the timing information, (c) receiving user input via an input device, the user input associated with an IC macro of the IC floorplan, (d) updating the timing information associated with the IC macro to generated updated timing information according to the user input, and (e) altering display of the representation according to the updated timing information.
摘要翻译： 一种方法包括：（a）由处理单元生成集成电路（IC）平面布置图的定时信息，（b）根据定时信息在显示设备上显示IC楼层布置图的表示，（c）经由 输入设备，与IC平面布置图的IC宏相关联的用户输入，（d）根据用户输入更新与IC宏关联的定时信息以生成更新的定时信息，以及（e）根据用户输入更改表示的显示 更新的定时信息。
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公开(公告)号：US12001773B2
公开(公告)日：2024-06-04
申请号：US18295085
申请日：2023-04-03
发明人： Shin-Chi Chen , King-Ho Tam , Yu-Ze Lin , Huang-Yu Chen
IPC分类号： G06F30/30 , G06F30/31 , G06F30/327 , G06F30/392 , G06F119/18
CPC分类号： G06F30/392 , G06F30/31 , G06F30/327 , G06F2119/18
摘要： A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device, subject to a limiting condition, such as one determined using a cost function. A computer system including one or more EDAs configured to perform the method is also disclosed.
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