公开(公告)号：US09871141B2

公开(公告)日：2018-01-16

申请号：US15090099

申请日：2016-04-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Carlos H. Diaz ,  Chih-Hao Wang ,  Gwan Sin Chang ,  Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/7849 ,  H01L21/02104 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A method includes performing a first epitaxy to grow a silicon germanium layer over a semiconductor substrate, performing a second epitaxy to grow a silicon layer over the silicon germanium layer, and performing a first oxidation to oxidize the silicon germanium layer, wherein first silicon germanium oxide regions are generated. A strain releasing operation is performed to release a strain caused by the first silicon germanium oxide regions. A gate dielectric is formed on a top surface and a sidewall of the silicon layer. A gate electrode is formed over the gate dielectric.

公开(公告)号：US09747402B2

公开(公告)日：2017-08-29

申请号：US14564934

申请日：2014-12-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Fung Song Lee ,  Wen-Ju Yang ,  Gwan Sin Chang ,  Yi-Kan Cheng ,  Li-Chun Tien ,  Lee-Chung Lu

IPC: H01L27/02 ,  G06F17/50 ,  H01L23/528 ,  H01L27/118

CPC classification number: G06F17/5072 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.

公开(公告)号：US20150132901A1

公开(公告)日：2015-05-14

申请号：US14557960

申请日：2014-12-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hao Wang ,  Kuo-Cheng Ching ,  Gwan Sin Chang ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L27/092

CPC classification number: H01L29/66818 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (S/D) regions separated by the gate region and a first fin structure in a gate region in the N-FET region. The first fin structure is formed by a first semiconductor material layer as a lower portion, a semiconductor oxide layer as a middle portion and a second semiconductor material layer as an upper portion. The semiconductor device also includes a second fin structure in S/D regions in the N-FET region. The second fin structure is formed by the first semiconductor material layer as a lower portion and the semiconductor oxide layer as a first middle portion, the first semiconductor material layer as a second middle portion beside the first middle and the second semiconductor material layer as an upper portion.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括具有由栅极区域分离的栅极区域，源极和漏极（S / D）区域以及N-FET区域中的栅极区域中的第一鳍状结构的衬底。 第一鳍结构由作为下部的第一半导体材料层，作为中间部分的半导体氧化物层和作为上部的第二半导体材料层形成。 半导体器件还包括在N-FET区域中的S / D区域中的第二鳍结构。 第二鳍结构由第一半导体材料层作为下部形成，半导体氧化物层作为第一中间部分，第一半导体材料层作为第一中间部分的第二中间部分，第二半导体材料层作为上部 一部分。

公开(公告)号：US08633516B1

公开(公告)日：2014-01-21

申请号：US13631688

申请日：2012-09-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zhiqiang Wu ,  Gwan Sin Chang ,  Kuo-Cheng Ching ,  Chun Chung Su ,  Shi Ning Ju

IPC: H01L29/66

CPC classification number: H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure provides a semiconductor device. The device includes a substrate, a fin structure formed by a first semiconductor material, a gate region on a portion of the fin, a source region and a drain region separated by the gate region on the substrate and a source/drain stack on the source and drain region. A low portion of the source/drain stack is formed by a second semiconductor material and it contacts a low portion of the fin in the gate region. An upper portion of the source/drain stack is formed by a third semiconductor material and it contacts an upper portion of the fin in the gate region.

Abstract translation: 本发明提供一种半导体器件。 该器件包括衬底，由第一半导体材料形成的鳍结构，鳍的一部分上的栅极区，由衬底上的栅极区分离的源极区和漏极区以及源极上的源极/漏极叠层 和漏极区。 源极/漏极堆叠的低部分由第二半导体材料形成，并且其在栅极区域中接触鳍片的低部分。 源极/漏极堆叠的上部由第三半导体材料形成，并且在栅极区域中接触鳍片的上部。

公开(公告)号：US09419098B2

公开(公告)日：2016-08-16

申请号：US14677612

申请日：2015-04-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Gwan Sin Chang ,  Zhiqiang Wu ,  Chih-Hao Wang ,  Carlos H. Diaz

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L29/165

CPC classification number: H01L29/7843 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785

Abstract: A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer is over the first silicon germanium oxide layer. The second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage. A gate dielectric is on sidewalls and a top surface of the semiconductor layer. A gate electrode is over the gate dielectric.

公开(公告)号：US20150129831A1

公开(公告)日：2015-05-14

申请号：US14599247

申请日：2015-01-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jean-Pierre Colinge ,  Gwan Sin Chang ,  Carlos H. Diaz

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/0676 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/7827 ,  H01L29/7843

Abstract: A device includes a semiconductor substrate and a vertical nano-wire over the semiconductor substrate. The vertical nano-wire includes a bottom source/drain region, a channel region over the bottom source/drain region, and a top source/drain region over the channel region. A top Inter-Layer Dielectric (ILD) encircles the top source/drain region. The device further includes a bottom ILD encircling the bottom source/drain region, a gate electrode encircling the channel region, and a strain-applying layer having vertical portions on opposite sides of, and contacting opposite sidewalls of, the top ILD, the bottom ILD, and the gate electrode.

Abstract translation: 一种器件包括半导体衬底和半导体衬底上的垂直纳米线。 垂直纳米线包括底部源极/漏极区域，在底部源极/漏极区域上的沟道区域，以及沟道区域上方的顶部源极/漏极区域。 顶层电介质（ILD）包围顶部源极/漏极区域。 该器件还包括环绕底部源极/漏极区域的底部ILD，环绕沟道区域的栅极电极以及在顶部ILD，底部ILD的相对侧和相对侧壁上具有垂直部分的应变施加层 ，和栅电极。

公开(公告)号：US08943445B2

公开(公告)日：2015-01-27

申请号：US14104279

申请日：2013-12-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pi-Tsung Chen ,  Ming-Hui Chih ,  Ken-Hsien Hsieh ,  Wei-Long Wang ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Wen-Ju Yang ,  Gwan Sin Chang ,  Yung-Sung Yen

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: A method includes determining one or more potential merges corresponding to a color set Ai and a color set Aj of N color sets, represented by A1 to AN, used in coloring polygons of a layout of an integrated circuit. N is a positive integer, i and j are integers from 1 to N, and i≠j. One or more potential cuts corresponding to the color set Ai and the second color set Aj are determined. An index Aij is determined according to the one or more potential merges and the one or more potential cuts. A plurality of parameters F related to the index Aij is obtained based on various values of indices fi and fj. A parameter F is selected among the plurality of parameters F based on a definition of the index Aij.

Abstract translation: 一种方法包括确定一个或多个与集成电路的布局的着色多边形中使用的颜色集合Ai和由A 1到AN表示的颜色集合A 1对应的潜在合并。 N是正整数，i和j是从1到N的整数，i≠j。 确定对应于颜色集合Ai和第二颜色集合Aj的一个或多个可能的剪切。 根据一个或多个潜在的合并和一个或多个潜在的切割来确定索引Aij。 基于索引fi和fj的各种值获得与索引Aij相关的多个参数F。 基于索引Aij的定义，在多个参数F中选择参数F.

公开(公告)号：US20140197457A1

公开(公告)日：2014-07-17

申请号：US13902322

申请日：2013-05-24

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Chih-Hao Wang ,  Kuo-Cheng Ching ,  Gwan Sin Chang ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66818 ,  H01L21/30604 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having isolation regions, a gate region, source and drain regions separated by the gate region, a first fin structure in a gate region. The first fin structure includes a first semiconductor material layer as a lower portion of the first fin structure, a semiconductor oxide layer as an outer portion of a middle portion of the first fin structure, the first semiconductor material layer as a center portion of the middle portion of the first fin structure and a second semiconductor material layer as an upper portion of the first fin structure. The semiconductor device also includes a source/drain feature over the substrate in the source/drain region between two adjacent isolation regions and a high-k (HK)/metal gate (MG) stack in the gate region, wrapping over a portion of the first fin structure.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括具有隔离区的衬底，栅极区，栅极区分离的源极和漏极区，栅极区中的第一鳍结构。 第一鳍结构包括作为第一鳍结构的下部的第一半导体材料层，作为第一鳍结构的中间部分的外部的半导体氧化物层，作为中间部分的中心部分的第一半导体材料层 第一鳍结构的一部分和作为第一鳍结构的上部的第二半导体材料层。 该半导体器件还包括位于两个相邻隔离区域之间的源极/漏极区域中的衬底上的源极/漏极特征以及栅极区域中的高k（HK）/金属栅极（MG） 第一鳍结构。

公开(公告)号：US09941404B2

公开(公告)日：2018-04-10

申请号：US15220700

申请日：2016-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Gwan Sin Chang ,  Zhiqiang Wu ,  Chih-Hao Wang ,  Carlos H. Diaz

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/775 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L29/7843 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785

Abstract: A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer is over the first silicon germanium oxide layer. The second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage. A gate dielectric is on sidewalls and a top surface of the semiconductor layer. A gate electrode is over the gate dielectric.

公开(公告)号：US20160233321A1

公开(公告)日：2016-08-11

申请号：US15130370

申请日：2016-04-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng Ching ,  Gwan Sin Chang ,  Zhiqiang Wu ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/306

CPC classification number: H01L29/66818 ,  H01L21/30604 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods are disclosed herein for fabricating integrated circuit devices, such as fin-like field-effect transistors (FinFETs). An exemplary method includes forming a first semiconductor material layer over a fin portion of a substrate; forming a second semiconductor material layer over the first semiconductor material layer; and converting a portion of the first semiconductor material layer to a first semiconductor oxide layer. The fin portion of the substrate, the first semiconductor material layer, the first semiconductor oxide layer, and the second semiconductor material layer form a fin. The method further includes forming a gate stack overwrapping the fin.

Abstract translation: 本文公开了用于制造诸如鳍状场效应晶体管（FinFET）的集成电路器件的方法。 一种示例性方法包括在衬底的翅片部分上形成第一半导体材料层; 在所述第一半导体材料层上形成第二半导体材料层; 以及将所述第一半导体材料层的一部分转换为第一半导体氧化物层。 基板的翅片部分，第一半导体材料层，第一半导体氧化物层和第二半导体材料层形成翅片。 该方法还包括形成包裹鳍片的栅叠层。