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    System, method and program for designing a semiconductor integrated circuit using standard cells
    13.
    发明申请
    System, method and program for designing a semiconductor integrated circuit using standard cells 审中-公开
    使用标准单元设计半导体集成电路的系统，方法和程序

    公开(公告)号：US20060236273A1

    公开(公告)日：2006-10-19

    申请号：US11392563

    申请日：2006-03-30

    申请人： Takeshi Ishigaki

    发明人： Takeshi Ishigaki

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/5072

    摘要： A computer implemented method for designing a semiconductor integrated circuit includes analyzing information of standard cells to be arranged in a chip area based on circuit behavior information so as to generate standard cell information, generating a mega cell including a group of standard cells, based on the standard cell information, and making a layout in which the same patterns repeat in the chip area by arranging a plurality of the mega cells having the same shape, throughout the chip area based on the circuit behavior information.

    摘要翻译： 一种用于设计半导体集成电路的计算机实现方法，包括基于电路行为信息分析要布置在芯片区域中的标准单元的信息，以便生成标准单元信息，基于该单元信息生成包括一组标准单元的兆字节单元 并且通过基于电路行为信息，在整个芯片区域中布置具有相同形状的多个兆字节单元来制作在芯片区域中重复相同图案的布局。

    Fault tolerant semiconductor system
    14.
    发明申请
    Fault tolerant semiconductor system 失效
    容错半导体系统

    公开(公告)号：US20050007143A1

    公开(公告)日：2005-01-13

    申请号：US10901035

    申请日：2004-07-29

    申请人： Takeshi Ishigaki

    发明人： Takeshi Ishigaki

    IPC分类号： G01R31/02 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/24 ,  G11C29/02 ,  H01L21/822 ,  H01L27/04 ,  G01R31/00 ,  G01R31/26

    CPC分类号： G06F11/24 ,  G01R31/2853 ,  G01R31/318505 ,  G01R31/318513 ,  G01R31/31855 ,  G11C29/02 ,  G11C29/025 ,  G11C2029/3202 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor system includes a plurality of semiconductor chips, a first group of wirings, a second group of wirings and a connection rearrange wiring section. The first group of wirings interconnect the plurality of semiconductor chips. The second group of wirings are used for redundancy and interconnect the plurality of semiconductor chips. The connection rearrange wiring section includes a connection test circuit and connection rearrange circuit. The connection test circuit makes a test for connection between the plurality of semiconductor chips by means of the first group of wirings. The connection rearrange circuit makes unusable a wiring of the first group in which poor connection occurs and rearranges the connection between the semiconductor chips by use of the wiring of the second group when the poor connection is detected in the wiring of the first group by the connection test circuit.

    摘要翻译： 半导体系统包括多个半导体芯片，第一组布线，第二组布线和连接重排布线部。 第一组布线将多个半导体芯片互连。 第二组布线被用于冗余并互连多个半导体芯片。 连接重新布线部分包括连接测试电路和连接重新布置电路。 连接测试电路通过第一组布线来测试多个半导体芯片之间的连接。 连接重新布置电路使得第一组的布线不可用，其中在第一组的布线中通过连接检测到不良连接时，通过使用第二组的布线来重新布置半导体芯片之间的连接 测试电路。

    Fault tolerant semiconductor system
    15.
    发明授权
    Fault tolerant semiconductor system 失效
    容错半导体系统

    公开(公告)号：US06788070B2

    公开(公告)日：2004-09-07

    申请号：US10162608

    申请日：2002-06-06

    申请人： Takeshi Ishigaki

    发明人： Takeshi Ishigaki

    IPC分类号： G01R3100

    CPC分类号： G06F11/24 ,  G01R31/2853 ,  G01R31/318505 ,  G01R31/318513 ,  G01R31/31855 ,  G11C29/02 ,  G11C29/025 ,  G11C2029/3202 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor system includes a plurality of semiconductor chips, a first group of wirings, a second group of wirings and a connection rearrange wiring section. The first group of wirings interconnect the plurality of semiconductor chips. The second group of wirings are used for redundancy and interconnect the plurality of semiconductor chips. The connection rearrange wiring section includes a connection test circuit and connection rearrange circuit. The connection test circuit makes a test for connection between the plurality of semiconductor chips by means of the first group of wirings. The connection rearrange circuit makes unusable a wiring of the first group in which poor connection occurs and rearranges the connection between the semiconductor chips by use of the wiring of the second group when the poor connection is detected in the wiring of the first group by the connection test circuit.

    摘要翻译： 半导体系统包括多个半导体芯片，第一组布线，第二组布线和连接重排布线部。 第一组布线将多个半导体芯片互连。 第二组布线用于冗余并互连多个半导体芯片。 连接重新布线部分包括连接测试电路和连接重新布置电路。 连接测试电路通过第一组布线来测试多个半导体芯片之间的连接。 连接重新布置电路使得第一组的布线不可用，其中在第一组的布线中通过连接检测到不良连接时，通过使用第二组的布线来重新布置半导体芯片之间的连接 测试电路。