公开(公告)号：US06427191B1

公开(公告)日：2002-07-30

申请号：US09224420

申请日：1998-12-31

申请人： John Wai Cheong Fu ,  Dean A. Mulla ,  Gregory S. Mathews

发明人： John Wai Cheong Fu ,  Dean A. Mulla ,  Gregory S. Mathews

IPC分类号： G06F1200

CPC分类号： G06F12/0846 ,  G06F12/0855

摘要： A novel on-chip cache memory and method of operation are provided which increase microprocessor performance. The cache design allows two cache requests to be processed simultaneously (dual-ported) and concurrent cache requests to be in-flight (pipelined). The design of the cache allocates a first clock cycle to cache tag and data access and a second cycle is allocated to data manipulation. The memory array circuit design is simplified because the circuits are synchronized to the main processor clock and do not need to use self-timed circuits. The overall logic control scheme is simplified because distinct cycles are allocated to the cache functions.

摘要翻译： 提供了一种新颖的片上缓存存储器和操作方法，其提高了微处理器的性能。 高速缓存设计允许两个缓存请求被同时处理（双端口）和并行缓存请求正在进行中（流水线）。 高速缓存的设计分配了第一个时钟周期来缓存标签和数据访问，第二个周期分配给数据操作。 存储器阵列电路设计被简化，因为电路与主处理器时钟同步，并且不需要使用自定时电路。 总体逻辑控制方案被简化，因为不同的周期被分配给缓存功能。

公开(公告)号：US06418521B1

公开(公告)日：2002-07-09

申请号：US09221230

申请日：1998-12-23

申请人： Gregory S. Mathews ,  Dean A. Mulla ,  John Wai Cheong Fu ,  Stuart E. Sailer

发明人： Gregory S. Mathews ,  Dean A. Mulla ,  John Wai Cheong Fu ,  Stuart E. Sailer

IPC分类号： G06F1208

CPC分类号： G06F12/126 ,  G06F12/1027 ,  G06F2212/681

摘要： A fully-associative translation lookaside buffer structure for a computer system includes a first-level TLB0 memory having a plurality of entries and a second-level TLB1 memory operatively coupled to the first level TLB0 memory. The second-level TLB1 memory also has a plurality of entries. Entries are placed in the TLB0 and TLB1 structure as a result of software controlled translation register operations and hardware controlled translation cache operations. Logic controlling TLB0 treats both operations the same way and uses a hardware replacement algorithm to determine the entry index. Logic controlling TLB1 uses a hardware replacement algorithm to determine the entry index for translation cache entries, and use an index provided within the insertion instruction to determine the entry index for translation register operations.

摘要翻译： 用于计算机系统的全关联翻译后备缓冲器结构包括具有多个条目的第一级TLB0存储器和可操作地耦合到第一级TLB0存储器的第二级TLB1存储器。 第二级TLB1存储器还具有多个条目。 作为软件控制的翻译寄存器操作和硬件控制的转换缓存操作的结果，条目被放置在TLB0和TLB1结构中。 逻辑控制TLB0以相同的方式对待操作，并使用硬件替换算法来确定入口索引。 逻辑控制TLB1使用硬件替换算法来确定转换缓存条目的入口索引，并使用插入指令中提供的索引来确定翻译寄存器操作的条目索引。

公开(公告)号：US06687262B1

公开(公告)日：2004-02-03

申请号：US09510280

申请日：2000-02-21

申请人： Daming Jin ,  Dean A. Mulla ,  Douglas J Cutter ,  Thomas Grutkowski

发明人： Daming Jin ,  Dean A. Mulla ,  Douglas J Cutter ,  Thomas Grutkowski

IPC分类号： H04J300

CPC分类号： G06F9/30043 ,  G06F9/30025 ,  G06F9/30032

摘要： The inventive control logic provides the selection signals for a bi-endian rotator MUX. The logic determines the starting point for the data transfer by determining which input register byte is going to Byte 0 of the output register. The control logic passes the starting point to single decoder. The decoded value is then sent to a plurality of MUXs, one for each of the output register bytes. Each of the MUXs is prewired to receive a portion of bits of the decoded value, and the portion is arranged in a particular order. The MUXs then send their respective outputs to the rotator MUX as selection control signals.

摘要翻译： 本发明的控制逻辑为双端旋转器MUX提供选择信号。 该逻辑通过确定哪个输入寄存器字节将转到输出寄存器的字节0来确定数据传输的起始点。 控制逻辑将起始点传递到单个解码器。 然后将解码的值发送到多个MUX，每个MUX为每个输出寄存器字节。 每个MUX被预接线以接收解码值的一部分位，并且该部分以特定顺序排列。 然后，多路复用器将其各自的输出发送到旋转器MUX作为选择控制信号。

公开(公告)号：US06470374B1

公开(公告)日：2002-10-22

申请号：US09510129

申请日：2000-02-21

申请人： Daming Jin ,  Dean A. Mulla ,  Tom Grutkowski

发明人： Daming Jin ,  Dean A. Mulla ,  Tom Grutkowski

IPC分类号： G06F750

CPC分类号： G06F7/508 ,  G06F9/3001 ,  G06F12/0895 ,  G06F2207/3832

摘要： The inventive adder can perform carry look-ahead calculations for a bi-endian adder in a cache memory system. The adder can add one of +/−1, 4, 8, or 16 to a loaded value from memory, and the operation can be a 4 or 8 byte add. The inventive adder comprises a plurality of byte adder cells and carry look-ahead (CLA) logic. The adder cells determine which of themselves is the least significant bit (LSB) byte adder cell. The LSB cell then adds one of the increment values to its loaded value. The other cells add 0x00 or 0xFF, depending upon the sign of the increment value, to a loaded value from memory. Each adder performs two adds, one for a carry-in of 0, and the other for a carry in of 1. Both results are sent to a MUX. The CLA logic determines each of the carries, and provides a selection control signal to each MUX. of the different cells.

摘要翻译： 本发明的加法器可以对高速缓冲存储器系统中的双端加法器进行执行预读计算。 加法器可以将+/- 1，4，8或16中的一个添加到存储器的加载值，并且操作可以是4或8字节加法。 本发明的加法器包括多个字节加法器单元和携带预读（CLA）逻辑。 加法器单元确定它们中的哪一个是最低有效位（LSB）字节加法器单元。 LSB单元然后将其中一个增量值添加到其加载值。 其他单元格根据增量值的符号将0x00或0xFF添加到内存中的加载值。 每个加法器执行两个加法，一个用于进位为0，另一个用于进位在1中。两个结果都发送到MUX。 CLA逻辑确定每个载波，并且向每个MUX提供选择控制信号。 的不同细胞。

公开(公告)号：US06453427B2

公开(公告)日：2002-09-17

申请号：US09224380

申请日：1998-12-31

申请人： Nhon T. Quach ,  John W. C. Fu ,  James O. Hays ,  Valentin Anders ,  Sorin Iacobovici ,  Alberto J. Munoz ,  Dean A. Mulla

发明人： Nhon T. Quach ,  John W. C. Fu ,  James O. Hays ,  Valentin Anders ,  Sorin Iacobovici ,  Alberto J. Munoz ,  Dean A. Mulla

IPC分类号： G06F1100

CPC分类号： G06F11/1044

摘要： An uncorrectable error is detected in the data of a computer system. The erroneous data is allowed to be stored in first and second caches of the computer system while the system runs first and second processes, the first process being associated with the data. The first process is terminated when an attempt is made to load the data from the cache. Meanwhile, the second process continues to run.

摘要翻译： 在计算机系统的数据中检测到不可校正的错误。 允许错误数据存储在计算机系统的第一和第二高速缓存中，同时系统运行第一和第二进程，第一进程与数据相关联。 尝试从缓存加载数据时，第一个进程终止。 同时，第二个过程继续运行。

公开(公告)号：US06408380B1

公开(公告)日：2002-06-18

申请号：US09316446

申请日：1999-05-21

申请人： Jerome C. Huck ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  David A. Fotland ,  Dean A. Mulla

发明人： Jerome C. Huck ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  David A. Fotland ,  Dean A. Mulla

IPC分类号： G06F9312

CPC分类号： G06F9/30043 ,  G06F9/30098 ,  G06F9/384

摘要： Method and apparatus for storing and executing an instruction to load two independent registers with two values is disclosed. In one embodiment, a computer-readable medium is encoded with an instruction including an opcode field specifying that the instruction is an instruction to load two independent registers with a first value and a second value, a source field specifying the first value and the second value, a first target register field specifying a first target register to load with the first value; a second target register field specifying a second target register to load with the second value. A system to execute the instruction is also disclosed.

摘要翻译： 公开了用于存储和执行用于加载具有两个值的两个独立寄存器的指令的方法和装置。 在一个实施例中，计算机可读介质用包括指定该指令是用于加载具有第一值和第二值的两个独立寄存器的指令的指令进行编码，指定第一值和第二值的源字段 指定第一目标寄存器以第一值加载的第一目标寄存器字段; 指定第二目标寄存器的第二目标寄存器字段，以加载第二值。 还公开了执行该指令的系统。

公开(公告)号：US06272597B1

公开(公告)日：2001-08-07

申请号：US09223847

申请日：1998-12-31

申请人： John Wai Cheong Fu ,  Dean A. Mulla ,  Gregory S. Mathews ,  Stuart E. Sailer

发明人： John Wai Cheong Fu ,  Dean A. Mulla ,  Gregory S. Mathews ,  Stuart E. Sailer

IPC分类号： G06F1210

CPC分类号： G06F12/0897

摘要： A novel on-chip cache memory and method of operation are provided which increase microprocessor performance. The on-chip cache memory has two levels. The first level is optimized for low latency and the second level is optimized for capacity. Both levels of cache are pipelined and can support simultaneous dual port accesses. A queuing structure is provided between the first and second level of cache which is used to decouple the faster first level cache from the slower second level cache. The queuing structure is also dual ported. Both levels of cache support non-blocking behavior. When there is a cache miss at one level of cache, both caches can continue to process other cache hits and misses. The first level cache is optimized for integer data. The second level cache can store any data type including floating point. The novel two-level cache system of the present invention provides high performance which emphasizes throughput.

摘要翻译： 提供了一种新颖的片上缓存存储器和操作方法，其提高了微处理器的性能。 片上高速缓存有两个级别。 第一级针对低延迟进行了优化，第二级针对容量进行了优化。 两级缓存都是流水线的，可以同时支持双端口访问。 在第一和第二级缓存之间提供排队结构，其用于将较快的第一级高速缓存与较慢的第二级高速缓存分离。 排队结构也是双端口的。 两级缓存支持非阻塞行为。 当一级缓存中存在高速缓存未命中时，两个缓存都可以继续处理其他缓存命中和丢失。 第一级缓存针对整数数据进行了优化。 第二级缓存可以存储包括浮点的任何数据类型。 本发明的新型二级缓存系统提供了强调吞吐量的高性能。

公开(公告)号：US06832308B1

公开(公告)日：2004-12-14

申请号：US09505249

申请日：2000-02-15

申请人： William G. Sicaras ,  Joe R. Butler ,  Don R. Weiss ,  Lakshmikant Mamileti ,  Reid J. Reidlinger ,  Dean A. Mulla

发明人： William G. Sicaras ,  Joe R. Butler ,  Don R. Weiss ,  Lakshmikant Mamileti ,  Reid J. Reidlinger ,  Dean A. Mulla

IPC分类号： G06F930

CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G06F9/3836

摘要： An apparatus is described comprising a signal indicative of which of a plurality of data structures stored in a queue desire to issue from the queue. The apparatus also has a content addressable memory having a plurality of cells, where each of the cells is configured to store one of the data structures. The apparatus also has an output from at least one of the cells that is indicative of whether the data structure within the at least one of the cells has issued from the queue. The apparatus also has an input to the at least one of the cells coupled to the signal.

摘要翻译： 描述了一种装置，其包括指示存储在队列中的多个数据结构中的哪一个期望从队列发出的信号。 该装置还具有内容可寻址存储器，其具有多个单元，其中每个单元被配置为存储数据结构之一。 该装置还具有来自至少一个小区的输出，其指示所述至少一个小区内的数据结构是否已经从队列发出。 该装置还具有至少一个与信号耦合的小区的输入。

公开(公告)号：US06647464B2

公开(公告)日：2003-11-11

申请号：US09507546

申请日：2000-02-18

申请人： Reid James Riedlinger ,  Dean A. Mulla ,  Tom Grutkowski

发明人： Reid James Riedlinger ,  Dean A. Mulla ,  Tom Grutkowski

IPC分类号： G06F1200

CPC分类号： G06F12/0855

摘要： A system and method are disclosed which provide a cache structure that allows early access to the cache structure's data. A cache design is disclosed that, in response to receiving a memory access request, begins an access to a cache level's data before a determination has been made as to whether a true hit has been achieved for such cache level. That is, a cache design is disclosed that enables cache data to be speculatively accessed before a determination is made as to whether a memory address required to satisfy a received memory access request is truly present in the cache. In a preferred embodiment, the cache is implemented to make a determination as to whether a memory address required to satisfy a received memory access request is truly present in the cache structure (i.e., whether a “true” cache hit is achieved). Although, such a determination is not made before the cache data begins to be accessed. Rather, in a preferred embodiment, a determination of whether a true cache hit is achieved in the cache structure is performed in parallel with the access of the cache structure's data. Therefore, a preferred embodiment implements a parallel path by beginning the cache data access while a determination is being made as to whether a true cache hit has been achieved. Thus, the cache data is retrieved early from the cache structure and is available in a timely manner for use by a requesting execution unit.

公开(公告)号：US06185660B2

公开(公告)日：2001-02-06

申请号：US08935681

申请日：1997-09-23

申请人： Dean A. Mulla ,  Sorin Iacobovici

发明人： Dean A. Mulla ,  Sorin Iacobovici

IPC分类号： G06F1200

CPC分类号： G06F9/30043 ,  G06F9/3824 ,  G06F12/0862 ,  G06F12/0875

摘要： An apparatus in a computer, called a pending access queue, for providing data for register load instructions after a cache miss. After a cache miss, when data is available for a register load instruction, the data is first directed to the pending access queue and is provided to an execution pipeline directly from the pending access queue, without requiring the data to be entered in the cache. Entries in the pending access queue include destination register identification, enabling injection of the data into the pipeline during intermediate pipeline phases. The pending access queue provides results to the requesting unit in any order needed, supporting out-of-order cache returns, and provides for arbitration when multiple sources have data ready to be processed. Each separate request to a single line is provided a separate entry, and each entry is provided with its appropriate part of the line as soon as the line is available, thereby rapidly providing data for multiple misses to a single line. The pending access queue may optionally include observability bits, enabling pending releases to complete execution before associated awaited data is present within the pending access queue. The pending access queue may optionally be used to include data to be stored by store instructions that have resulted in a cache miss.

摘要翻译： 计算机中的设备，称为未决访问队列，用于在缓存未命中之后提供用于寄存器加载指令的数据。 在缓存未命中之后，当数据可用于寄存器加载指令时，数据首先被定向到等待访问队列，并且直接从挂起的访问队列提供给执行流水线，而不需要将数据输入缓存。 待处理访问队列中的条目包括目标寄存器标识，可以在中间流水线阶段将数据注入流水线。 待处理的访问队列以所需的任何顺序向请求单元提供结果，支持无序高速缓存返回，并且当多个源具有准备好处理的数据时，提供仲裁。 对单个线路的每个单独请求都提供了单独的条目，并且一旦该线路可用，则每个条目都被提供有线路的适当部分，从而快速向单个线路提供多个未命中的数据。 挂起的访问队列可以可选地包括可观察性位，使等待的版本能够在等待访问队列中存在相关联的等待数据之前完成执行。 等待访问队列可以可选地用于包括由导致高速缓存未命中的存储指令存储的数据。