公开(公告)号：US06427191B1

公开(公告)日：2002-07-30

申请号：US09224420

申请日：1998-12-31

申请人： John Wai Cheong Fu ,  Dean A. Mulla ,  Gregory S. Mathews

发明人： John Wai Cheong Fu ,  Dean A. Mulla ,  Gregory S. Mathews

IPC分类号： G06F1200

CPC分类号： G06F12/0846 ,  G06F12/0855

摘要： A novel on-chip cache memory and method of operation are provided which increase microprocessor performance. The cache design allows two cache requests to be processed simultaneously (dual-ported) and concurrent cache requests to be in-flight (pipelined). The design of the cache allocates a first clock cycle to cache tag and data access and a second cycle is allocated to data manipulation. The memory array circuit design is simplified because the circuits are synchronized to the main processor clock and do not need to use self-timed circuits. The overall logic control scheme is simplified because distinct cycles are allocated to the cache functions.

摘要翻译： 提供了一种新颖的片上缓存存储器和操作方法，其提高了微处理器的性能。 高速缓存设计允许两个缓存请求被同时处理（双端口）和并行缓存请求正在进行中（流水线）。 高速缓存的设计分配了第一个时钟周期来缓存标签和数据访问，第二个周期分配给数据操作。 存储器阵列电路设计被简化，因为电路与主处理器时钟同步，并且不需要使用自定时电路。 总体逻辑控制方案被简化，因为不同的周期被分配给缓存功能。

公开(公告)号：US06418521B1

公开(公告)日：2002-07-09

申请号：US09221230

申请日：1998-12-23

申请人： Gregory S. Mathews ,  Dean A. Mulla ,  John Wai Cheong Fu ,  Stuart E. Sailer

发明人： Gregory S. Mathews ,  Dean A. Mulla ,  John Wai Cheong Fu ,  Stuart E. Sailer

IPC分类号： G06F1208

CPC分类号： G06F12/126 ,  G06F12/1027 ,  G06F2212/681

摘要： A fully-associative translation lookaside buffer structure for a computer system includes a first-level TLB0 memory having a plurality of entries and a second-level TLB1 memory operatively coupled to the first level TLB0 memory. The second-level TLB1 memory also has a plurality of entries. Entries are placed in the TLB0 and TLB1 structure as a result of software controlled translation register operations and hardware controlled translation cache operations. Logic controlling TLB0 treats both operations the same way and uses a hardware replacement algorithm to determine the entry index. Logic controlling TLB1 uses a hardware replacement algorithm to determine the entry index for translation cache entries, and use an index provided within the insertion instruction to determine the entry index for translation register operations.

摘要翻译： 用于计算机系统的全关联翻译后备缓冲器结构包括具有多个条目的第一级TLB0存储器和可操作地耦合到第一级TLB0存储器的第二级TLB1存储器。 第二级TLB1存储器还具有多个条目。 作为软件控制的翻译寄存器操作和硬件控制的转换缓存操作的结果，条目被放置在TLB0和TLB1结构中。 逻辑控制TLB0以相同的方式对待操作，并使用硬件替换算法来确定入口索引。 逻辑控制TLB1使用硬件替换算法来确定转换缓存条目的入口索引，并使用插入指令中提供的索引来确定翻译寄存器操作的条目索引。

公开(公告)号：US06272597B1

公开(公告)日：2001-08-07

申请号：US09223847

申请日：1998-12-31

申请人： John Wai Cheong Fu ,  Dean A. Mulla ,  Gregory S. Mathews ,  Stuart E. Sailer

发明人： John Wai Cheong Fu ,  Dean A. Mulla ,  Gregory S. Mathews ,  Stuart E. Sailer

IPC分类号： G06F1210

CPC分类号： G06F12/0897

摘要： A novel on-chip cache memory and method of operation are provided which increase microprocessor performance. The on-chip cache memory has two levels. The first level is optimized for low latency and the second level is optimized for capacity. Both levels of cache are pipelined and can support simultaneous dual port accesses. A queuing structure is provided between the first and second level of cache which is used to decouple the faster first level cache from the slower second level cache. The queuing structure is also dual ported. Both levels of cache support non-blocking behavior. When there is a cache miss at one level of cache, both caches can continue to process other cache hits and misses. The first level cache is optimized for integer data. The second level cache can store any data type including floating point. The novel two-level cache system of the present invention provides high performance which emphasizes throughput.

摘要翻译： 提供了一种新颖的片上缓存存储器和操作方法，其提高了微处理器的性能。 片上高速缓存有两个级别。 第一级针对低延迟进行了优化，第二级针对容量进行了优化。 两级缓存都是流水线的，可以同时支持双端口访问。 在第一和第二级缓存之间提供排队结构，其用于将较快的第一级高速缓存与较慢的第二级高速缓存分离。 排队结构也是双端口的。 两级缓存支持非阻塞行为。 当一级缓存中存在高速缓存未命中时，两个缓存都可以继续处理其他缓存命中和丢失。 第一级缓存针对整数数据进行了优化。 第二级缓存可以存储包括浮点的任何数据类型。 本发明的新型二级缓存系统提供了强调吞吐量的高性能。

公开(公告)号：US6105115A

公开(公告)日：2000-08-15

申请号：US1742

申请日：1997-12-31

申请人： Gregory S. Mathews ,  Dean A. Mulla

发明人： Gregory S. Mathews ,  Dean A. Mulla

IPC分类号： G06F12/12 ,  G06F12/00

CPC分类号： G06F12/124 ,  G06F12/126 ,  G06F12/128

摘要： A NRU algorithm is used to track lines in each region of a memory array such that the corresponding NRU bits are reset on a region-by-region basis. That is, the NRU bits of one region are reset when all of the bits in that region indicate that their corresponding lines have recently been used. Similarly, the NRU bits of another region are reset when all of the bits in that region indicate that their corresponding lines have recently been used. Resetting the NRU bits in one region, however, does not affect the NRU bits in another region. A LRU algorithm is used to track the regions of the array such that each region has a single corresponding entry in a LRU table. That is, all the lines in a single region collectively correspond to a single LRU entry. A region is elevated to most recently used status in the LRU table once the NRU bits of the region are reset.

摘要翻译： 使用NRU算法来跟踪存储器阵列的每个区域中的线，使得相应的NRU位在逐个区域的基础上被重置。 也就是说，当该区域中的所有位表示最近已经使用了相应的行时，一个区域的NRU位被复位。 类似地，当该区域中的所有位指示它们的相应行最近被使用时，另一区域的NRU位被复位。 然而，复位一个区域中的NRU位不影响另一个区域中的NRU位。 使用LRU算法来跟踪阵列的区域，使得每个区域在LRU表中具有单个对应的条目。 也就是说，单个区域中的所有行共同对应于单个LRU条目。 一旦该区域的NRU位复位，区域就被提升到LRU表中最近使用的状态。

公开(公告)号：US06557078B1

公开(公告)日：2003-04-29

申请号：US09510283

申请日：2000-02-21

申请人： Dean A. Mulla ,  Terry L Lyon ,  Reid James Riedlinger ,  Thomas Grutkowski

发明人： Dean A. Mulla ,  Terry L Lyon ,  Reid James Riedlinger ,  Thomas Grutkowski

IPC分类号： G06F1300

CPC分类号： G06F12/0855 ,  G06F12/0851 ,  G06F12/1054

摘要： The inventive cache uses a queuing structure which provides out-of-order cache memory access support for multiple accesses, as well as support for managing bank conflicts and address conflicts. The inventive cache can support four data accesses that are hits per clocks, support one access that misses the L1 cache every clock, and support one instruction access every clock. The responses are interspersed in the pipeline, so that conflicts in the queue are minimized. Non-conflicting accesses are not inhibited, however, conflicting accesses are held up until the conflict clears. The inventive cache provides out-of-order support after the retirement stage of a pipeline.

摘要翻译： 本发明的高速缓存使用排队结构，其为多个访问提供无序高速缓存存储器访问支持，以及用于管理银行冲突和地址冲突的支持。 本发明的高速缓存可以支持每个时钟命中的四个数据访问，支持每个时钟丢失L1缓存的一个访问，并且每个时钟支持一个指令访问。 响应散布在流水线中，从而使队列中的冲突最小化。 不冲突的访问不被禁止，但冲突的冲突消除之后，冲突的访问将被阻止。 本发明的缓存在管道的退役阶段之后提供无序支持。

公开(公告)号：US06427189B1

公开(公告)日：2002-07-30

申请号：US09510973

申请日：2000-02-21

申请人： Dean A. Mulla ,  Reid James Riedlinger ,  Tom Grutkowski

发明人： Dean A. Mulla ,  Reid James Riedlinger ,  Tom Grutkowski

IPC分类号： G06F1300

CPC分类号： G06F12/0846 ,  G06F12/0897

摘要： A multi-level cache structure and associated method of operating the cache structure are disclosed. The cache structure uses a queue for holding address information for a plurality of memory access requests as a plurality of entries. The queue includes issuing logic for determining which entries should be issued. The issuing logic further comprises find first logic for determining which entries meet a predetermined criteria and selecting a plurality of those entries as issuing entries. The issuing logic also comprises lost logic that delays the issuing of a selected entry for a predetermined time period based upon a delay criteria. The delay criteria may, for example, comprise a conflict between issuing resources, such as ports. Thus, in response to an issuing entry being oversubscribed, the issuing of such entry may be delayed for a predetermined time period (e.g., one clock cycle) to allow the resource conflict to clear.

摘要翻译： 公开了一种操作高速缓存结构的多级缓存结构和相关联的方法。 高速缓存结构使用用于将多个存储器访问请求的地址信息保存为多个条目的队列。 队列包括用于确定应该发出哪些条目的发布逻辑。 发布逻辑还包括找到用于确定哪些条目符合预定标准的第一逻辑，并且选择多个这些条目作为发行条目。 发布逻辑还包括基于延迟准则延迟所选条目发布预定时间段的丢失逻辑。 延迟标准可以例如包括发布诸如端口的资源之间的冲突。 因此，响应于超额认购的发行条目，这样的条目的发布可以延迟预定时间段（例如，一个时钟周期），以允许资源冲突清除。

公开(公告)号：US5696939A

公开(公告)日：1997-12-09

申请号：US536534

申请日：1995-09-29

申请人： Sorin Iacobovici ,  Dean A. Mulla

发明人： Sorin Iacobovici ,  Dean A. Mulla

IPC分类号： G06F15/16 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/52 ,  G06F12/08 ,  G06F15/177 ,  G06F12/00

CPC分类号： G06F9/3834 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3885 ,  G06F9/52

摘要： A simplified semaphore method and apparatus for simultaneous execution of multiple semaphore instructions and for enforcement of necessary ordering. A central processing unit having an instruction pipeline is coupled with a data cache arrangement including a semaphore buffer, a data cache, and the semaphore execution unit. An initial semaphore instruction having one or more operands and a semaphore address are transmitted from the instruction pipeline to the semaphore buffer, which in turn are transmitted from the semaphore buffer to the semaphore execution unit. The semaphore address of the initial semaphore instruction is transmitted from the instruction pipeline to the data cache to retrieve initial semaphore data stored within the data cache at a location in a data line of the data cache as identified by the semaphore address. The semaphore instruction is executed within the semaphore execution unit by operating upon the initial semaphore data and the one or more semaphore operands so as to produce processed semaphore data, which is then stored within the data cache. Since the semaphore buffer provides for entries of multiple semaphore instructions, the semaphore buffer initiates simultaneous execution of multiple semaphore instructions, as needed.

摘要翻译： 用于同时执行多个信号量指令并执行必要排序的简化信号量方法和装置。 具有指令流水线的中央处理单元与包括信号量缓冲器，数据高速缓存和信号量执行单元的数据高速缓存装置耦合。 具有一个或多个操作数和信号量地址的初始信号量指令从指令流水线发送到信号量缓冲器，信号量缓冲器又从信号量缓冲器发送到信号量执行单元。 初始信号量指令的信号量地址从指令流水线发送到数据高速缓存，以在信号量地址识别的数据高速缓存的数据行中的位置检索存储在数据高速缓存内的初始信号量数据。 信号量指令通过操作初始信号量数据和一个或多个信号量操作数在信号量执行单元内执行，以产生处理后的信号量数据，然后存储在数据高速缓存中。 由于信号量缓冲器提供多个信号量指令的条目，因此信号量缓冲区根据需要启动多个信号量指令的同时执行。

公开(公告)号：US06826573B1

公开(公告)日：2004-11-30

申请号：US09504205

申请日：2000-02-15

申请人： William G. Sicaras ,  Dean A. Mulla

发明人： William G. Sicaras ,  Dean A. Mulla

IPC分类号： G06F700

CPC分类号： G06F5/10 ,  G06F9/3802 ,  G06F2205/106 ,  Y10S707/99931

摘要： A method of generating an issue pointer for issuing data structures from a queue, comprising generating a signal that indicates where one or more of the data structures within the queue that desire to issue are located within the queue. Then, checking the signal at a queue location pointed to by an issue pointer. Then, incrementing the position of the issue pointer if a data structure has not shifted into the queue location since the previous issue and if the issue pointer is pointing to the location having issued on the previous queue issue or holding the issue pointer position if a data structure has shifted into the location since the previous issue and if the issue pointer is pointing to the location having issued on the previous queue issue.

摘要翻译： 一种生成用于从队列发布数据结构的问题指针的方法，包括生成指示队列内的一个或多个数据结构位于队列内的信号。 然后，检查由问题指针指向的队列位置处的信号。 然后，如果数据结构自上一个问题以来，如果数据结构没有转入队列位置，并且如果问题指针指向已发布在先前队列问题上的位置，或者如果数据存在，则增加问题指针的位置 结构已经从上一个问题转移到该位置，并且如果问题指针指向在先前队列问题上发布的位置。

公开(公告)号：US06539457B1

公开(公告)日：2003-03-25

申请号：US09510279

申请日：2000-02-21

申请人： Dean A. Mulla ,  Reid James Riedlinger ,  Thomas Grutkowski

发明人： Dean A. Mulla ,  Reid James Riedlinger ,  Thomas Grutkowski

IPC分类号： G06F1200

CPC分类号： G06F12/0897

摘要： The inventive cache manages address conflicts and maintains program order without using a store buffer. The cache utilizes an issue algorithm to insure that accesses issued in the same clock are actually issued in an order that is consistent with program order. This is enabled by performing address comparisons prior to insertion of the accesses into the queue. Additionally, when accesses are separated by one or more clocks, address comparisons are performed, and accesses that would get data from the cache memory array before a prior update has actually updated the cache memory in the array are canceled. This provides a guarantee that program order is maintained, as an access is not allowed to complete until it is assured that the most recent data will be received upon access of the array.

摘要翻译： 本发明的缓存管理地址冲突并维护程序顺序而不使用存储缓冲器。 缓存利用问题算法来确保在同一时钟内发出的访问实际上是按照与程序顺序一致的顺序发出的。 这可以通过在将访问插入队列之前执行地址比较来实现。 此外，当访问被一个或多个时钟分开时，执行地址比较，并且取消在先前更新之前从高速缓存存储器阵列获取数据实际更新数组中的高速缓冲存储器的访问。 这提供了保证程序顺序的保证，因为访问不允许完成，直到确保在数组访问时将接收到最新的数据。

公开(公告)号：US06427188B1

公开(公告)日：2002-07-30

申请号：US09501396

申请日：2000-02-09

申请人： Terry L Lyon ,  Eric R DeLano ,  Dean A. Mulla

发明人： Terry L Lyon ,  Eric R DeLano ,  Dean A. Mulla

IPC分类号： G06F1200

CPC分类号： G06F12/0864 ,  G06F12/0884 ,  G06F12/0897 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

摘要： A system and method are disclosed which determine in parallel for multiple levels of a multi-level cache whether any one of such multiple levels is capable of satisfying a memory access request. Tags for multiple levels of a multi-level cache are accessed in parallel to determine whether the address for a memory access request is contained within any of the multiple levels. For instance, in a preferred embodiment, the tags for the first level of cache and the tags for the second level of cache are accessed in parallel. Also, additional levels of cache tags up to N levels may be accessed in parallel with the first-level cache tags. Thus, by the end of the access of the first-level cache tags it is known whether a memory access request can be satisfied by the first-level, second-level, or any additional N-levels of cache that are accessed in parallel. Additionally, in a preferred embodiment, the multi-level cache is arranged such that the data array of a level of cache is accessed only if it is determined that such level of cache is capable of satisfying a received memory access request. Additionally, in a preferred embodiment the multi-level cache is partitioned into N ways of associativity, and only a single way of a data array is accessed to satisfy a memory access request, thereby preserving the remaining ways of a data array to save power and resources that may be accessed to satisfy other instructions.

摘要翻译： 公开了一种系统和方法，其并行地确定多级高速缓存的多个级别，无论这样的多个级别中的任何一个是否能够满足存储器访问请求。 并行访问多级高速缓存的多级别的标签，以确定存储器访问请求的地址是否包含在多个级别中的任一级内。 例如，在优选实施例中，并行地访问用于第一级高速缓存的标签和用于第二级高速缓存的标签。 此外，可以与第一级缓存标签并行访问高达N级的缓存标签的附加级别。 因此，通过第一级缓存标签的访问结束，已知存储器访问请求是否可以由并行访问的高级缓存的第一级，第二级或任何附加N级满足。 此外，在优选实施例中，多级缓存被布置成使得仅当确定这种级别的高速缓存能够满足所接收的存储器访问请求时才能访问高速缓存级的数据阵列。 此外，在优选实施例中，多级缓存被分为N个关联方式，并且仅访问数据阵列的单一方式以满足存储器访问请求，从而保留数据阵列的剩余方式以节省功率， 可以访问的资源以满足其他指令。