公开(公告)号：US09152586B2

公开(公告)日：2015-10-06

申请号：US14056775

申请日：2013-10-17

Applicant: Texas Instruments Incorporated

Inventor： Daniel B Wu ,  Matthew D Pierson ,  Kai Chirca ,  Timothy D Anderson

IPC: G06F13/16 ,  G06F13/40 ,  G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

Abstract translation: 为了能够有效跟踪事务，使用确认期望信号来给缓存一致互连提供一个交易是否需要连贯的所有权跟踪的提示。 该信号通知高速缓存相干互连，以便在读/写传输完成时期望来自发起主机的所有权转移确认信号。 因此，高速缓存相干互连可以在其一致性点继续跟踪事务，直到在必要时从发起主机接收到确认。

公开(公告)号：US09372808B2

公开(公告)日：2016-06-21

申请号：US14059732

申请日：2013-10-22

Applicant: Texas Instruments Incorporated

Inventor： Matthew D Pierson ,  Daniel B Wu ,  Kai Chirca

IPC: G06F12/08 ,  G06F12/10 ,  G06F13/16 ,  H04L29/06 ,  G06F13/42 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: This invention mitigates these deadlocking issues by a adding a separate non-blocking pipeline for snoop returns. This separate pipeline would not be blocked behind coherent requests. This invention also repartitions the master initiated traffic to move cache evictions (both with and without data) and non-coherent writes to the new non-blocking channel. This non-blocking pipeline removes the need for any coherent requests to complete before the snoop request can reach the memory controller. Repartitioning cache initiated evictions to the non-blocking pipeline prevents deadlock when snoop and eviction occur concurrently. The non-blocking channel of this invention combines snoop responses from memory controller initiated requests and master initiated evictions/non-coherent writes.

Abstract translation: 本发明通过为窥探返回添加单独的非阻塞管道来缓解这些死锁问题。 这个单独的管道不会被阻塞在一致的请求之后。 本发明还重新分配主发起的流量以移动高速缓存驱逐（包括和不具有数据）和非相干写入到新的非阻塞信道。 这种非阻塞管道消除了在侦听请求到达内存控制器之前需要完成的任何一致的请求。 重新分区高速缓存启动的撤回到非阻塞管道可以同时发生侦听和撤离时防止死锁。 本发明的非阻塞信道组合来自存储器控制器发起的请求和主发起的驱逐/非相干写入的窥探响应。

公开(公告)号：US09372799B2

公开(公告)日：2016-06-21

申请号：US14841956

申请日：2015-09-01

Applicant: Texas Instruments Incorporated

Inventor： Daniel B Wu ,  Matthew D Pierson ,  Kai Chirca ,  Timothy D Anderson

IPC: G06F13/00 ,  G06F12/08 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

公开(公告)号：US09304925B2

公开(公告)日：2016-04-05

申请号：US14061508

申请日：2013-10-23

Applicant: Texas Instruments Incorporated

Inventor： Kai Chirca ,  Matthew D Pierson

IPC: G06F13/00 ,  G06F12/08 ,  G06F12/02 ,  G06F11/22 ,  G06F13/16

CPC classification number: G06F12/0831 ,  G06F11/2289 ,  G06F12/0284 ,  G06F13/1668 ,  G06F13/1673 ,  G06F2212/6042

Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. Each processor has an associated return buffer allowing out of order responses of memory read data and cache snoop responses to ensure maximum bandwidth at the endpoints, and all endpoints receive status messages to simplify the return queue.

Abstract translation: 描述的MSMC（多核共享内存控制器）是一种旨在管理多处理器内核，其他母盘外设或DMA之间的流量的模块，以及多核SoC中的EMIF（外部存储器间隔）。 每个处理器都有一个关联的返回缓冲区，允许存储器读取数据和高速缓存侦听响应的无序响应，以确保端点处的最大带宽，并且所有端点接收状态消息以简化返回队列。

公开(公告)号：US09213656B2

公开(公告)日：2015-12-15

申请号：US14061470

申请日：2013-10-23

Applicant: Texas Instruments Incorporated

Inventor： Kai Chirca ,  Matthew D Pierson

IPC: G06F13/00 ,  G06F13/16 ,  G06F11/10

CPC classification number: G06F12/084 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0683 ,  G06F11/1064 ,  G06F13/1652 ,  G06F13/1668 ,  G06F2212/1016 ,  G06F2212/60

Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.

Abstract translation: 描述的MSMC（多核共享存储器控制器）是一种旨在管理多处理器内核，其他母盘外设或DMA之间流量的模块，以及多核SoC中的EMIF（外部存储器间隔）。 本发明在仲裁事务之前统一属于从属方的所有事务大小，以便降低仲裁过程的复杂性，并在所有主机之间提供最佳的带宽管理。 每个缓存行访问分配两个连续的插槽，以自动保证单个高速缓存行内所有事务的原子性。 消除了对特定SRAM的所有存储体之间同步的需要，因为通过分配背靠背槽来实现同步。

公开(公告)号：US09129071B2

公开(公告)日：2015-09-08

申请号：US14057205

申请日：2013-10-18

Applicant: Texas Instruments Incorporated

Inventor： Matthew D Pierson ,  Kai Chirca ,  Timothy D Anderson

IPC: G06F12/08 ,  G06F13/42 ,  G06F13/16 ,  H04L29/06

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: This invention speeds operation for coherence writes to shared memory. This invention immediately commits to the memory endpoint coherence write data. Thus this data will be available earlier than if the memory controller stalled this write pending snoop responses. This invention computes write enable strobes for the coherence write data based upon the cache dirty tags. This invention initiates a snoop cycle based upon the address of the coherence write. The stored write enable strobes enable determination of which data to write to the endpoint memory upon a cached and dirty snoop response.

Abstract translation: 本发明加速了对共享存储器的一致性写操作。 本发明立即提交到存储器端点一致写入数据。 因此，如果内存控制器停止了这个写入挂起的侦听响应，那么这个数据将可用。 本发明基于高速缓存脏标签计算用于相干写入数据的写入使能选通。 本发明基于一致性写入的地址启动窥探循环。 存储的写使能选通使得能够确定在高速缓存和脏的窥探响应时哪些数据写入端点存储器。

公开(公告)号：US09075928B2

公开(公告)日：2015-07-07

申请号：US14059774

申请日：2013-10-22

Applicant: Texas Instruments Incorporated

Inventor： Matthew D Pierson ,  Kai Chirca

IPC: G06F12/00 ,  G06F13/42 ,  G06F12/08 ,  G06F13/16 ,  H04L29/06

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A coherence maintenance address queue tracks each memory access from receipt until the memory reports the access complete. The address of each new access is compared against the address of all entries in the queue. This check is made when the access is ready to transmit to the memory. If there is no address match, then the current access does not conflict with any pending access. If there is an address match, the current access is stalled. The multi-core shared memory controller would then typically proceed to another access waiting a slot to the endpoint memory. Stored addresses in the coherence maintenance address queue are retired when the endpoint memory reports completion of the operation. At this point the access is no longer a hazard to following operations.

Abstract translation: 一致性维护地址队列跟踪从收到的每个内存访问，直到内存报告访问完成。 将每个新访问的地址与队列中所有条目的地址进行比较。 当访问准备好传输到内存时进行此检查。 如果没有地址匹配，则当前访问不会与任何未决访问冲突。 如果地址匹配，则当前访问被停止。 然后，多核共享存储器控制器将通常进行到等待端口存储器的时隙的另一访问。 当端点存储器报告操作完成时，相干维护地址队列中存储的地址将被停用。 在这一点上，访问不再对以下操作构成危害。

公开(公告)号：US20140115266A1

公开(公告)日：2014-04-24

申请号：US14056775

申请日：2013-10-17

Applicant: Texas Instruments Incorporated

Inventor： Daniel B Wu ,  Matthew D Pierson ,  Kai Chirca ,  Timothy D Anderson

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

Abstract translation: 为了能够有效跟踪事务，使用确认期望信号来给缓存一致互连提供一个交易是否需要连贯的所有权跟踪的提示。 该信号通知高速缓存相干互连，以便在读/写传输完成时期望来自发起主机的所有权转移确认信号。 因此，高速缓存相干互连可以在其一致性点继续跟踪事务，直到在必要时从发起主机接收到确认。