公开(公告)号：US20150370710A1

公开(公告)日：2015-12-24

申请号：US14841956

申请日：2015-09-01

Applicant: Texas Instruments Incorporated

Inventor： Daniel B. Wu ,  Matthew D. Pierson ,  Kai Chirca ,  Timothy D. Anderson

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

Abstract translation: 为了能够有效跟踪事务，使用确认期望信号来给缓存一致互连提供一个交易是否需要连贯的所有权跟踪的提示。 该信号通知高速缓存相干互连，以便在读/写传输完成时期望来自发起主机的所有权转移确认信号。 因此，高速缓存相干互连可以在其一致性点继续跟踪事务，直到在必要时从发起主机接收到确认。

公开(公告)号：US20150082004A1

公开(公告)日：2015-03-19

申请号：US14327002

申请日：2014-07-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mujibur Rahman ,  Djordje Senicic ,  Timothy D. Anderson

IPC: G06F9/30

CPC classification number: H04N19/56 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3853 ,  G06F9/3893 ,  G06F2207/5442 ,  H04N19/433 ,  H04N19/521

Abstract: This invention is a digital signal processor form plural sums of absolute values (SAD) in a single operation. An operational unit performing a sum of absolute value operation comprising two sets of a plurality of rows, each row producing a SAD output. Plural absolute value difference units receive corresponding packed candidate pixel data and packed reference pixel data. A row summer sums the output of the absolute value difference units in the row. The candidate pixels are offset relative to the reference pixels by one pixel for each succeeding row in a set of rows. The two sets of rows operate on opposite halves of the candidate pixels packed within an instruction specified operand. The SAD operations can be performed on differing data widths employing carry chain control in the absolute difference unit and the row summers.

Abstract translation: 本发明是在单个操作中形成多个绝对值（SAD）的数字信号处理器。 执行包括两组多行的绝对值操作之和的操作单元，每行产生SAD输出。 多个绝对值差分单元接收相应的压缩候选像素数据和压缩参考像素数据。 行夏天对行中的绝对值差单位的输出求和。 候选像素相对于参考像素相对于一组行中的每个后续行偏移一个像素。 两组行在包含在指令指定操作数中的候选像素的相对的两半上进行操作。 可以使用绝对差分单位和行夏季的进位链控制在不同的数据宽度上执行SAD操作。

公开(公告)号：US12223327B2

公开(公告)日：2025-02-11

申请号：US18487186

申请日：2023-10-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Duc Bui ,  Joseph Zbiciak ,  Reid E. Tatge

IPC: G06F9/38

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

公开(公告)号：US12197917B2

公开(公告)日：2025-01-14

申请号：US17849994

申请日：2022-06-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Timothy D. Anderson ,  David E. Smith, Jr. ,  Paul D. Gauvreau

IPC: G06F9/38 ,  G06F9/30

Abstract: A computer-implemented method includes fetching a fetch-packet containing a first hyper-block from a first address of a memory. The fetch-packet contains a bitwise distance from an entry point of the first hyper-block to a predicted exit point. A first branch instruction of the first hyper-block is executed that corresponds to a first exit point. The first branch instruction includes an address corresponding to an entry point of a second hyper-block. Responsive to executing the first branch instruction, a bitwise distance from the entry point of the first hyper-block to the first exit point is stored. A program counter is moved from the first exit point of the first hyper-block to the entry point of the second hyper-block.

公开(公告)号：US12175244B2

公开(公告)日：2024-12-24

申请号：US18507222

申请日：2023-11-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L. Davis

IPC: G06F9/30

Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

公开(公告)号：US20240320004A1

公开(公告)日：2024-09-26

申请号：US18670855

申请日：2024-05-22

Applicant: Texas Instruments Incorporated

Inventor： Duc Bui ,  Peter Richard Dent ,  Timothy D. Anderson

IPC: G06F9/30

CPC classification number: G06F9/3013 ,  G06F9/30036 ,  G06F9/30105

Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

公开(公告)号：US12032961B2

公开(公告)日：2024-07-09

申请号：US18191066

申请日：2023-03-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Bui ,  Peter Richard Dent ,  Timothy D. Anderson

IPC: G06F9/30

CPC classification number: G06F9/3013 ,  G06F9/30036 ,  G06F9/30105

Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

公开(公告)号：US20240036866A1

公开(公告)日：2024-02-01

申请号：US18355939

申请日：2023-07-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Bui ,  Timothy D. Anderson ,  Paul Gauvreau

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3802 ,  G06F9/3836

Abstract: Disclosed herein are systems and methods for executing multiple instruction set architectures (ISAs) on a singular processing unit. In an implementation, a processor that includes a first decoder, a second decoder, instruction fetch circuitry, and instruction dispatch circuitry is configured to execute two separate instruction set architectures. In an implementation, the instruction fetch circuitry is configured to fetch instructions from an associated memory. In an implementation the instruction dispatch circuitry is coupled to the instruction fetch circuitry, the first decoder, and the second decoder and is configured to route instructions associated with a first ISA to the first decoder, and route instructions associated with a second ISA to the second decoder.

公开(公告)号：US20230367598A1

公开(公告)日：2023-11-16

申请号：US18191066

申请日：2023-03-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Bui ,  Peter Richard Dent ,  Timothy D. Anderson

IPC: G06F9/30

CPC classification number: G06F9/3013 ,  G06F9/30105 ,  G06F9/30036

Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

公开(公告)号：US11816485B2

公开(公告)日：2023-11-14

申请号：US17367384

申请日：2021-07-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L. Davis

IPC: G06F9/30

CPC classification number: G06F9/30065 ,  G06F9/3013

Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.