Z-compression mechanism
    13.
    发明授权
    Z-compression mechanism 有权
    Z压缩机制

    公开(公告)号:US06580427B1

    公开(公告)日:2003-06-17

    申请号:US09608950

    申请日:2000-06-30

    IPC分类号: G06T1700

    CPC分类号: G06T15/405

    摘要: A graphics system is provided to implement compression of depth or z-data. The graphic system includes a buffer, a status table, and a read/write unit. The buffer stores depth data for multiple blocks of pixels in associated buffer entries. The status table stores status values for the entries of the buffer. The status value for a given entry indicates an access mode for the corresponding depth data according to whether the data is compressed, uncompressed or in a reference state. The read/write unit implements data accesses for a given entry responsive to the status value associated with the entry.

    摘要翻译: 提供图形系统来实现深度或z数据的压缩。 图形系统包括缓冲器,状态表和读/写单元。 缓冲器存储相关缓冲区条目中多个像素块的深度数据。 状态表存储缓冲区条目的状态值。 根据数据是压缩的,未压缩的还是参考状态,给定条目的状态值表示对应的深度数据的访问模式。 读取/写入单元响应于与条目相关联的状态值来实现给定条目的数据访问。

    Recoverable parity and residue error
    14.
    发明授权
    Recoverable parity and residue error 有权
    可恢复奇偶校验和残差误差

    公开(公告)号:US08909988B2

    公开(公告)日:2014-12-09

    申请号:US13436319

    申请日:2012-03-30

    IPC分类号: G06F11/00

    CPC分类号: G06F11/1405 G06F11/1032

    摘要: An error recovery unit that may include error logic to detect an error in a dispatch port and timestamp logic configured to generate a timestamp for the error. The error recovery unit may also include check logic to determine if an instruction associated with the error has been retired based on the timestamp. If the instruction has been retired, a machine check error logic may be initiated. If the instruction has not been retired, an error correction logic may be initiated to recover the error and to re-execute the instruction. Thus, speculative errors may be recovered without the need for calling the machine check error, which is undesirable because of its catastrophic nature. Therefore, machine check errors may be significantly reduced.

    摘要翻译: 错误恢复单元,其可以包括用于检测调度端口中的错误的错误逻辑和被配置为生成错误的时间戳的时间戳逻辑。 错误恢复单元还可以包括检查逻辑,以基于时间戳来确定与错误相关联的指令是否已经退休。 如果指令已经停止,则可能启动机器检查错误逻辑。 如果指令还没有退出,则可以启动纠错逻辑来恢复错误并重新执行指令。 因此,可以恢复投机错误,而不需要调用机器检查错误,这是因为其灾难性质而不期望的。 因此,机器检查错误可能会显着降低。

    CONDITIONAL MEMORY FAULT ASSIST SUPPRESSION
    15.
    发明申请
    CONDITIONAL MEMORY FAULT ASSIST SUPPRESSION 有权
    条件记忆障碍协助抑制

    公开(公告)号:US20150261590A1

    公开(公告)日:2015-09-17

    申请号:US14214910

    申请日:2014-03-15

    IPC分类号: G06F11/07

    摘要: In some disclosed embodiments instruction execution logic provides conditional memory fault assist suppression. Some embodiments of processors comprise a decode stage to decode one or more instruction specifying: a set of memory operations, one or more register, and one or more memory address. One or more execution units, responsive to the one or more decoded instruction, generate said one or more memory address for the set of memory operations. Instruction execution logic records one or more fault suppress bits to indicate whether one or more portion of the set of memory operations are masked. Fault generation logic is suppressed from considering a memory fault corresponding to a faulting one of the set of memory operations when said faulting one of the set of memory operations corresponds to a portion of the set of memory operations that is indicated as masked by said one or more fault suppress bits.

    摘要翻译: 在一些公开的实施例中,指令执行逻辑提供条件存储器故障辅助抑制。 处理器的一些实施例包括解码级,以对一个或多个指令进行解码,该指令指定:一组存储器操作,一个或多个寄存器和一个或多个存储器地址。 响应于一个或多个解码指令的一个或多个执行单元为该组存储器操作生成所述一个或多个存储器地址。 指令执行逻辑记录一个或多个故障抑制位以指示该组存储器操作中的一个或多个部分被屏蔽。 当所述一组存储器操作中的所述故障之一对应于由所述一组存储器操作屏蔽的所述一组存储器操作的一部分时,故障产生逻辑被抑制为考虑与所述一组存储器操作中的故障的一个存储器操作相对应的存储器故障, 更多的故障抑制位。

    Fused multiply add operations using bit masks
    17.
    发明授权
    Fused multiply add operations using bit masks 有权
    融合乘法使用位掩码添加操作

    公开(公告)号:US09542154B2

    公开(公告)日:2017-01-10

    申请号:US13926175

    申请日:2013-06-25

    IPC分类号: G06F7/483 G06F7/544 G06F7/76

    摘要: Systems and methods of performing a fused multiply add (FMA) operations are provided. In one embodiment, the length of the adder used by the FMA operation is less than 3*N, where N is the number of bits in the mantissa term of a floating point number. A mask may be used to perform the addition portion of the FMA operation using the adder. A second mask may be used to denormalize the result of the addition portion of the FMA operation if an underflow occurs.

    摘要翻译: 提供了执行融合乘法(FMA)操作的系统和方法。 在一个实施例中,由FMA操作使用的加法器的长度小于3 * N,其中N是浮点数的尾数项中的位数。 可以使用掩码来使用加法器来执行FMA操作的相加部分。 如果发生下溢,则可以使用第二掩模来对FMA操作的添加部分的结果进行非规范化。

    APPARATUS AND METHOD FOR PERFORMING A PERMUTE OPERATION
    18.
    发明申请
    APPARATUS AND METHOD FOR PERFORMING A PERMUTE OPERATION 有权
    用于执行操作的装置和方法

    公开(公告)号:US20150026440A1

    公开(公告)日:2015-01-22

    申请号:US13996072

    申请日:2011-12-23

    IPC分类号: G06F9/30

    摘要: An apparatus and method are described for permuting data elements with masking. For example, a method according to one embodiment includes the following operations: reading values from a mask data structure to determine whether masking is implemented for each data element of a destination operand; if masking not implemented for a particular data element, then selecting data elements from the destination operand and a second source operand based on index values stored in a first source operand to be copied to data element positions within the destination operand, wherein any one of the data elements from either the destination operand and the second source operand may be copied to any one of the data element positions within the destination operand; if masking is implemented for a particular data element of the destination operand, then performing a designated masking operation with respect to that particular data element.

    摘要翻译: 描述了用掩模来置换数据元素的装置和方法。 例如,根据一个实施例的方法包括以下操作:从掩模数据结构读取值以确定是否对目的地操作数的每个数据元素实施掩蔽; 如果对特定数据元素没有实现掩蔽,则根据存储在第一源操作数中的索引值从目的地操作数和第二源操作数中选择要复制到目的地操作数内的数据元素位置的第二源操作数,其中, 来自目的地操作数和第二源操作数的数据元素可以被复制到目的地操作数中的任何一个数据元素位置; 如果针对目的地操作数的特定数据元素实现掩蔽,则对该特定数据元素执行指定的屏蔽操作。