公开(公告)号：US06642804B2

公开(公告)日：2003-11-04

申请号：US10074578

申请日：2002-02-13

申请人： Ioannis Chrissostomidis ,  Thoai-Thai Le

发明人： Ioannis Chrissostomidis ,  Thoai-Thai Le

IPC分类号： H03L700

CPC分类号： H03K3/0231 ,  H03K3/011

摘要： The invention creates an oscillator circuit, in particular for a refresh timer device of a dynamic semiconductor memory, having a capacitor device (C; C′) which is connected between a first node (6) and a first supply potential (P2); a current mirror circuit (T1; T2) for supplying a charging current for the capacitor device (C; C′) which is connected via a first transistor device (T4) to the first node (6) and which has a current source (SQ) for supplying a substantially temperature-independent reference current (Iref); a second transistor device (T5), which is connected between the first node (6) and the first supply potential (P2); the first and second transistor devices (T4; T5) and a control signal being configured in such a way that the capacitor device (C; C′) can be charged via the first node (6) when a potential (Vcomp) at the first node (6) is lower than the reference potential (Vref), and can be discharged via the first node (6) when the potential (Vcomp) at the first node (6) is higher than the reference potential (Vref) such that the signal at an output (A) oscillates.

摘要翻译： 本发明创建了一种振荡器电路，特别是用于动态半导体存储器的刷新定时器装置，其具有连接在第一节点（6）和第一电源电位（P2）之间的电容器装置（C; C'）; 用于为经由第一晶体管器件（T4）连接到第一节点（6）并且具有电流源（SQ）的电容器器件（C; C'）提供充电电流的电流镜电路（T1; T2） ），用于提供基本上温度无关的参考电流（Iref）; 连接在第一节点（6）和第一电源电位（P2）之间的第二晶体管器件（T5）; 第一和第二晶体管器件（T4; T5）和控制信号被配置成使得当第一和第二晶体管器件（T4; T5）的电位（V comp） 节点（6）低于参考电位（Vref），并且当第一节点（6）处的电位（Vcomp）高于参考电位（Vref）时，可以经由第一节点（6）放电， 输出（A）的信号振荡。

公开(公告)号：US6125073A

公开(公告)日：2000-09-26

申请号：US391717

申请日：1999-09-08

申请人： Thoai-Thai Le ,  Jurgen Lindolf ,  Eckhard Brass ,  Martin Brox

发明人： Thoai-Thai Le ,  Jurgen Lindolf ,  Eckhard Brass ,  Martin Brox

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C8/08 ,  G11C11/401 ,  G11C8/00

CPC分类号： G11C5/14 ,  G11C8/08

摘要： In an integrated semiconductor memory having a memory cell array divided into memory banks, supply potentials with high drive capability are applied to the memory banks only if the respective memory bank is activated for access to a memory cell. For this purpose a supply voltage assigned to the respective memory bank is controlled by the same address signal as the memory bank. The supply voltage sources generate a word line potential, a bit line potential or a substrate potential. As a result, a power loss is reduced.

摘要翻译： 在具有划分为存储体的存储单元阵列的集成半导体存储器中，只有当相应的存储体被激活以访问存储单元时，具有高驱动能力的电源才被施加到存储体。 为此，分配给相应存储体的电源电压由与存储体相同的地址信号控制。 电源电压源产生字线电位，位线电位或衬底电位。 结果，功率损耗降低。

公开(公告)号：US06696872B1

公开(公告)日：2004-02-24

申请号：US10252331

申请日：2002-09-23

申请人： Thoai-Thai Le ,  Torsten Partsch

发明人： Thoai-Thai Le ,  Torsten Partsch

IPC分类号： H03L706

CPC分类号： G06F1/10 ,  H03L7/0814 ,  Y10S331/02

摘要： A delay locked loop (DLL) for use in a semiconductor device includes a phase detector that receives a reference clock signal and a feedback clock signal and provides a delay control signal to a latch. The latch provides a latched delay control signal to a delay circuit. The delay circuit receives the reference clock signal in addition to the latched delay control signal, and provides a delayed clock signal. An off chip driver (OCD) receives the delayed clock signal and provides an interim feedback clock signal to a receiver. The receiver provides the feedback clock signal to the phase detector, thus completing the loop. The DLL may also include a means for receiving and responding to an update command, wherein the update command causes loop to open, and the latch to store the delay control signal.

摘要翻译： 用于半导体器件的延迟锁定环（DLL）包括相位检测器，其接收参考时钟信号和反馈时钟信号，并向锁存器提供延迟控制信号。 锁存器向延迟电路提供锁存的延迟控制信号。 延迟电路除了锁存的延迟控制信号之外还接收参考时钟信号，并提供延迟的时钟信号。 片外驱动器（OCD）接收延迟的时钟信号，并向接收机提供中间反馈时钟信号。 接收器将反馈时钟信号提供给相位检测器，从而完成循环。 DLL还可以包括用于接收和响应更新命令的装置，其中更新命令使得环路打开，并且锁存器存储延迟控制信号。

公开(公告)号：US06477099B2

公开(公告)日：2002-11-05

申请号：US09761815

申请日：2001-01-16

申请人： Helmut Fischer ,  Sebastian Kuhne ,  Thoai-Thai Le

发明人： Helmut Fischer ,  Sebastian Kuhne ,  Thoai-Thai Le

IPC分类号： G11C702

CPC分类号： H03F3/45183

摘要： An integrated circuit has a differential amplifier in a basic circuit having two input transistors, a load element and a power source. The power source has an N-type channel MOS transistor whose controlled path is connected to the input transistors and to a supply terminal of the power source. A control terminal of the transistor is connected to a potential that is positive with respect to a reference potential. The supply terminal of the power source is connected to a potential which is negative with respect to the reference potential and which is made available by a voltage source for switching off cell field transistors of a DRAM memory. The gate-source voltage that is increased in this way improves the behavior of the circuit with respect to fluctuations in potential and permits more favorable dimensioning of the transistor.

摘要翻译： 集成电路在具有两个输入晶体管，负载元件和电源的基本电路中具有差分放大器。 电源具有N型沟道MOS晶体管，其受控路径连接到输入晶体管和电源的供电端子。 晶体管的控制端子连接到相对于参考电位为正的电位。 电源的供电端子连接到相对于参考电位为负的电位，并且由用于关断DRAM存储器的单元场晶体管的电压源可用。 以这种方式增加的栅极 - 源极电压改善了电路相对于电位波动的行为，并且允许晶体管的更有利的尺寸。

公开(公告)号：US06456553B1

公开(公告)日：2002-09-24

申请号：US09898233

申请日：2001-07-03

申请人： Eckhard Brass ,  Thoai-Thai Le ,  Jürgen Lindolf ,  Joachim Schnabel

发明人： Eckhard Brass ,  Thoai-Thai Le ,  Jürgen Lindolf ,  Joachim Schnabel

IPC分类号： G11C700

CPC分类号： G11C11/406 ,  G11C7/22 ,  G11C11/4074

摘要： A circuit configuration for switching over a receiver circuit, in particular in DRAM memories, between a standby mode and an operating mode, includes a differential amplifier functioning as a receiver receiving a control voltage derived from a reference current and generated or fed in for setting a correct operating point of said differential amplifier. A line feeds a current for generating the control voltage. Switching elements are disposed in said line for each receiver. The switching elements are permanently closed in the operating mode by an enable signal present at said switching elements for continuously supplying the current for generating the control voltage. The switching elements are closed at discrete times or periodically in the standby mode by feeding a refresh signal for discontinuously refreshing the control voltage. A DRAM memory having the circuit configuration is also provided.

摘要翻译： 用于在待机模式和操作模式之间切换接收器电路，特别是在DRAM存储器中的电路配置包括：差分放大器，用作接收从参考电流导出并产生或进给的控制电压的接收器，用于设置 所述差分放大器的正确工作点。 线路馈送用于产生控制电压的电流。 开关元件设置在每个接收器的所述线中。 开关元件在操作模式下通过存在于所述开关元件处的使能信号永久闭合，以连续地供应用于产生控制电压的电流。 开关元件在离散时间或在待机模式下周期性地闭合，通过馈送用于不连续地刷新控制电压的刷新信号。 还提供了具有电路结构的DRAM存储器。

公开(公告)号：US06215351B1

公开(公告)日：2001-04-10

申请号：US09321174

申请日：1999-05-27

申请人： Thoai-Thai Le ,  Helmut Schneider

发明人： Thoai-Thai Le ,  Helmut Schneider

IPC分类号： H01H3776

CPC分类号： G11C17/18 ,  G11C17/16

摘要： A fuse-latch circuit in which, by use of a first and a second control signal, which are staggered over time with respect to one another, fuse information can be read from a fuse into a latch element and can be stored in the latch element. Both control signals are in this case obtained from only one global signal by a delay element.

摘要翻译： 一种熔丝锁存电路，其中通过使用第一和第二控制信号，它们相对于彼此随时间而交错，熔丝信息可以从熔丝读取到锁存元件中并且可以被存储在锁存元件中 。 在这种情况下，两个控制信号仅由延迟元件仅由一个全局信号获得。

公开(公告)号：US06188634B1

公开(公告)日：2001-02-13

申请号：US09505379

申请日：2000-02-16

申请人： Thoai-Thai Le

发明人： Thoai-Thai Le

IPC分类号： G11C812

CPC分类号： G11C8/12

摘要： In semiconductor memories, memory banks are activated via memory bank decoders. The memory bank decoders assigned to different groups of memory banks have a layout that is symmetrical with respect to an axis of mirror symmetry. A changeover is made between the memory bank decoders by a predecoder. For this purpose, the predecoder generates enable and address signals for the memory banks. This enables the memory bank decoders to be disposed on the semiconductor chip in direct proximity to the respectively assigned memory banks.

摘要翻译： 在半导体存储器中，通过存储体解码器激活存储体。 分配给不同组存储体的存储体解码器具有相对于镜像对称轴对称的布局。 通过预解码器在存储体解码器之间进行切换。 为此，预解码器为存储体生成使能和地址信号。 这使得存储体解码器能够直接靠近分配的存储体设置在半导体芯片上。

公开(公告)号：US06920523B2

公开(公告)日：2005-07-19

申请号：US10265964

申请日：2002-10-07

申请人： Thoai-Thai Le ,  Stephen Bowyer

发明人： Thoai-Thai Le ,  Stephen Bowyer

IPC分类号： G06F1/32 ,  G06F12/00 ,  G06F12/06 ,  G06F12/08 ,  G11C11/406

CPC分类号： G06F1/3203 ,  G06F1/3275 ,  G06F12/06 ,  G06F12/0846 ,  G06F12/0893 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14

摘要： A system and method for refreshing data in a dynamic random access memory (“DRAM”) is provided, where the system includes a data memory having a plurality of memory banks, a map memory in signal communication with the data memory for translating an internal address of each of the plurality of memory banks into a corresponding external address, a map comparator in signal communication with the map memory for selectively enabling a memory bank in accordance with its external address, a refresh address generator in signal communication with the map comparator for selectively refreshing the enabled memory bank in accordance with its external address, and a refresh counter in signal communication with the refresh address generator for signaling a refresh in accordance with the maximum required refresh time of the enabled memory bank; and where the corresponding method includes determining the maximum required refresh period for each of the memory banks, respectively, prioritizing the memory banks in accordance with their respective refresh periods, utilizing the memory banks in order of their respective prioritizations, selectively disabling at least one of the memory banks in reverse-order of their respective prioritizations, and refreshing only the remaining non-disabled memory banks.

摘要翻译： 提供了一种用于在动态随机存取存储器（“DRAM”）中刷新数据的系统和方法，其中系统包括具有多个存储体的数据存储器，与数据存储器进行信号通信的地图存储器，用于翻译内部地址 多个存储体中的每一个存储为相应的外部地址;映射比较器，与地图存储器进行信号通信，用于根据其外部地址选择性地使能存储体;与地图比较器进行信号通信的刷新地址生成器， 根据其外部地址刷新启用的存储体，以及与刷新地址生成器进行信号通信的刷新计数器，用于根据所启用的存储体的最大所需刷新时间来发信号通知刷新; 并且其中相应的方法包括分别确定每个存储体的最大所需刷新周期，根据它们各自的刷新周期对存储体进行优先排序，按照它们各自的优先次序按顺序利用存储体，选择性地禁用 存储器组以其各自的优先级的相反顺序，并仅刷新剩余的非残留存储体。

公开(公告)号：US06721215B2

公开(公告)日：2004-04-13

申请号：US10185628

申请日：2002-06-28

申请人： Thoai-Thai Le ,  Jürgen Lindolf

发明人： Thoai-Thai Le ,  Jürgen Lindolf

IPC分类号： G11C700

CPC分类号： G11C29/88 ,  G11C29/883

摘要： An integrated dynamic memory includes a memory cell array having memory cells each assigned to one of a plurality of groups. The plurality of groups are divided into defect-free groups having exclusively defect-free memory cells and into defective groups having at least one defective memory cell. The memory further includes a memory configuration table that contains a list of the defect-free groups and an assignment unit that, based upon the entries in the memory configuration table, executes memory accesses only to those memory cells assigned to a defect-free group. The total capacity of the memory module, then, is not fixed once and for all with fabrication, but, rather, results only after a memory test, or may even vary in the course of the module lifetime.

摘要翻译： 集成动态存储器包括具有每个分配给多个组中的一个组的存储单元的存储单元阵列。 将这些组分成具有无缺陷存储单元的无缺陷组，并将其分成具有至少一个缺陷存储单元的缺陷组。 存储器还包括存储器配置表，其包含无缺陷组的列表，以及分配单元，其基于存储器配置表中的条目仅对分配给无缺陷组的存储器单元执行存储器访问。 然后，存储器模块的总容量一劳永逸地固定在一起，而是仅在存储器测试之后才能得到结果，或者甚至可能在模块寿命的过程中变化。

公开(公告)号：US06476650B2

公开(公告)日：2002-11-05

申请号：US10005944

申请日：2001-12-03

申请人： Thoai-Thai Le

发明人： Thoai-Thai Le

IPC分类号： H03B100

CPC分类号： H03K19/00361

摘要： A method and also a circuit configuration with a driver circuit for the parallel amplification of two input signals is described. A first and a second amplified output signal respectively are formed from the input signals, in which case, in the event of a change in the amplitudes of the two input signals in a predetermined time period, the first output signal is changed with a first temporal gradient in a first time period and is then changed with a second gradient in a second time period, and in which case the second output signal is changed with a third temporal gradient in a third time period and is then changed with a fourth temporal gradient in a fourth time period.