公开(公告)号：US06717200B1

公开(公告)日：2004-04-06

申请号：US09408688

申请日：1999-09-30

申请人： Florian Schamberger ,  Helmut Schneider ,  Jürgen Lindolf ,  Thoai-Thai Le

发明人： Florian Schamberger ,  Helmut Schneider ,  Jürgen Lindolf ,  Thoai-Thai Le

IPC分类号： H01L31119

CPC分类号： H01L29/66666 ,  H01L21/26586 ,  H01L29/42368 ,  H01L29/7827

摘要： A vertical MOS field effect transistor includes a gate disposed in a trench, a channel, and a source and a drain disposed in the substrate on the trench wall. The gate annularly surrounds a drain terminal which extends from the substrate surface as far as the drain disposed on the trench bottom. It is possible to produce vertical transistors with different channel lengths on a substrate with trenches of different widths by employing oblique implantation when producing the gate. A method of producing the vertical field effect transistor is also provided.

摘要翻译： 垂直MOS场效应晶体管包括设置在沟槽中的栅极，沟道以及设置在沟槽壁上的衬底中的源极和漏极。 栅极环形地围绕从衬底表面延伸到漏极设置在沟槽底部的漏极端子。 通过在制造栅极时采用倾斜注入，可以在具有不同宽度的沟槽的衬底上制造具有不同沟道长度的垂直晶体管。 还提供了一种制造垂直场效应晶体管的方法。

公开(公告)号：US06215351B1

公开(公告)日：2001-04-10

申请号：US09321174

申请日：1999-05-27

申请人： Thoai-Thai Le ,  Helmut Schneider

发明人： Thoai-Thai Le ,  Helmut Schneider

IPC分类号： H01H3776

CPC分类号： G11C17/18 ,  G11C17/16

摘要： A fuse-latch circuit in which, by use of a first and a second control signal, which are staggered over time with respect to one another, fuse information can be read from a fuse into a latch element and can be stored in the latch element. Both control signals are in this case obtained from only one global signal by a delay element.

摘要翻译： 一种熔丝锁存电路，其中通过使用第一和第二控制信号，它们相对于彼此随时间而交错，熔丝信息可以从熔丝读取到锁存元件中并且可以被存储在锁存元件中 。 在这种情况下，两个控制信号仅由延迟元件仅由一个全局信号获得。

公开(公告)号：US06181624B2

公开(公告)日：2001-01-30

申请号：US09398695

申请日：1999-09-20

申请人： Thoai-Thai Le ,  J{umlaut over (u)}rgen Lindolf ,  Helmut Schneider

发明人： Thoai-Thai Le ,  J{umlaut over (u)}rgen Lindolf ,  Helmut Schneider

IPC分类号： G11C708

CPC分类号： G11C7/06 ,  G11C8/08 ,  G11C8/18 ,  G11C11/4091

摘要： An integrated memory has memory cells disposed in a cell array at crossover points of bit lines and word lines for storing information items. In addition, the memory has a word line decoder by which the word lines can be addressed, and at least one evaluation unit for evaluating the information items read from the memory cells onto the bit lines and the evaluation unit has an activation input. In addition, the integrated memory has a logic unit for performing an OR function and has inputs connected to that end of each of the word lines which is remote from the word line decoder. The logic unit further has an output connected to the activation input of the evaluation unit. The logic unit serves for time-optimized activation of the evaluation unit as soon as one of the word lines has been selected by the word line decoder.

摘要翻译： 集成存储器具有位于单元阵列中的存储单元，位于位线和字线的交叉点处，用于存储信息项。 此外，存储器具有可以寻址字线的字线解码器，并且至少一个用于评估从存储器单元读取到位线上的信息项的评估单元和评估单元具有激活输入。 此外，集成存储器具有用于执行OR功能的逻辑单元，并且具有连接到远离字线解码器的每个字线的端部的输入。 逻辑单元还具有连接到评估单元的激活输入的输出。 一旦字线解码器选择了一个字线，该逻辑单元用于评估单元的时间优化激活。

公开(公告)号：US06756655B2

公开(公告)日：2004-06-29

申请号：US10013298

申请日：2001-12-10

申请人： Thoai-Thai Le ,  Jürgen Lindolf

发明人： Thoai-Thai Le ,  Jürgen Lindolf

IPC分类号： H01L2900

CPC分类号： H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor configuration is described which includes a semiconductor body having a main surface and an insulator layer disposed on the main surface of the semiconductor body. The insulator layer has a cavity formed therein extending to the main surface of the semiconductor body. A fuse having a fusible part extends from the main surface of the semiconductor body toward an upper surface of the insulator layer at right angles to the main surface of the semiconductor body, and the fuse is embedded in the cavity. A method for producing the semiconductor configuration having the fuse is also described.

摘要翻译： 描述了一种半导体结构，其包括具有设置在半导体主体的主表面上的主表面和绝缘体层的半导体本体。 绝缘体层具有形成在其中的空腔，其延伸到半导体本体的主表面。 具有可熔部分的保险丝从半导体本体的主表面朝着与半导体主体的主表面成直角的绝缘体层的上表面延伸，并且保险丝嵌入在腔中。 还描述了具有熔丝的半导体结构的制造方法。

公开(公告)号：US06970395B2

公开(公告)日：2005-11-29

申请号：US10658130

申请日：2003-09-08

申请人： Thoai-Thai Le ,  Ralf Klein ,  Eckhard Brass ,  George Alexander

发明人： Thoai-Thai Le ,  Ralf Klein ,  Eckhard Brass ,  George Alexander

IPC分类号： G11C7/10 ,  G11C11/4076 ,  G11C8/00

CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C2207/2281

摘要： A memory device includes a delay-locked loop circuit having delay elements and a synchronization circuit coupled to the delay-locked loop circuit. The synchronization circuit receives a synchronization enable signal and outputs a plurality of enable signals, including an enable signal coupled to an output circuit. Because the enable signal is synchronized with the read signal, it is possible to provide more time to read data into the buffer. A method of reading data from a memory device couples a synchronization enable signal and an external clock signal to a synchronization circuit. A read signal and an output enable are generated based upon a synchronization enable signal and a delayed clock signal of the external clock signal. Because the output signal is synchronized to the read signal, more time is allowed for the sense function.

摘要翻译： 存储器件包括具有延迟元件的延迟锁定环路电路和耦合到延迟锁定环路电路的同步电路。 同步电路接收同步使能信号并输出​​多个使能信号，包括耦合到输出电路的使能信号。 由于使能信号与读取信号同步，所以可以提供更多的时间将数据读入缓冲器。 从存储器件读取数据的方法将同步使能信号和外部时钟信号耦合到同步电路。 基于外部时钟信号的同步使能信号和延迟的时钟信号，产生读取信号和输出使能。 由于输出信号与读取信号同步，所以允许感应功能更多的时间。

公开(公告)号：US06389086B1

公开(公告)日：2002-05-14

申请号：US09521396

申请日：2000-03-08

申请人： Thoai-Thai Le ,  Eckhard Brass ,  Markus Biebl

发明人： Thoai-Thai Le ,  Eckhard Brass ,  Markus Biebl

IPC分类号： H03B110

CPC分类号： H03K5/1252

摘要： A digital circuit has a signal input terminal and a signal output terminal. The digital circuit additionally has a logic circuit unit, whose input is connected to the signal input terminal and whose output is connected to the signal output terminal via a switching element. Furthermore, it has a filter unit, whose input is connected to the signal input terminal and whose output is connected to a control input of the switching element. The filter unit serves for suppressing glitches on a digital signal present at its input.

摘要翻译： 数字电路具有信号输入端和信号输出端。 数字电路还具有逻辑电路单元，其输入端连接到信号输入端子，其输出端经由开关元件连接到信号输出端子。 此外，它具有滤波器单元，其输入端连接到信号输入端，并且其输出端连接到开关元件的控制输入端。 滤波器单元用于抑制存在于其输入端的数字信号的毛刺。

公开(公告)号：US06838917B2

公开(公告)日：2005-01-04

申请号：US10266354

申请日：2002-10-07

申请人： Eckhard Brass ,  Bernd Klehn ,  Ralf Klein ,  Thoai-Thai Le

发明人： Eckhard Brass ,  Bernd Klehn ,  Ralf Klein ,  Thoai-Thai Le

IPC分类号： G11C7/10 ,  G11C7/22 ,  H03L7/06

CPC分类号： G11C7/1066 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222

摘要： A circuit configuration for processing data, particularly a semiconductor memory chip, has a control circuit for setting a phase or frequency relationship between two signals. A digital counter detects a phase or frequency difference between the two signals, and the counter reading is used for regulating the phase or frequency relationship. Trials have shown that the counter reading indicates an operating state in the circuit configuration and therefore represents a simple signal for assessing the operating state of the circuit configuration. Preferably, the counter reading is taken as a basis for adjusting the speed or power of time-critical or performance-critical circuit parts in the circuit configuration so that an operating state with an intermediate switching speed is obtained.

摘要翻译： 用于处理数据的电路配置，特别是半导体存储器芯片，具有用于设置两个信号之间的相位或频率关系的控制电路。 数字计数器检测两个信号之间的相位或频率差，并且计数器读数用于调节相位或频率关系。 试验表明，计数器读数表示电路配置中的工作状态，因此表示用于评估电路配置工作状态的简单信号。 优选地，计数器读数作为调整电路配置中时间关键或性能关键电路部件的速度或功率的基础，从而获得具有中间切换速度的操作状态。

公开(公告)号：US06717447B1

公开(公告)日：2004-04-06

申请号：US10271955

申请日：2002-10-15

申请人： Thoai-Thai Le ,  Ralf Klein

发明人： Thoai-Thai Le ,  Ralf Klein

IPC分类号： H03L700

CPC分类号： H03L7/0814 ,  H03K2005/00058 ,  H03K2005/00234

摘要： A delay adjustment circuit for decreasing a phase shift between a system clock and a feedback clock from a semiconductor's internal clock. The circuit includes a difference-pulse generator that provides an interim clock 180 degrees out of phase with the feedback clock when the feedback clock is leading the system clock, and equal to the feedback clock otherwise. The difference-pulse generator also provides a difference-pulse signal that is at logic high for a period of time by which the system clock and an inversion of the interim clock are phase shifted. The circuit also includes a delay control unit and a delay unit which delay the interim clock by the period of time. The resulting delayed interim clock, which is 180 degrees out of phase with the system clock, is inverted to provide an internal clock in phase with the system clock.

摘要翻译： 一种延迟调整电路，用于减少来自半导体内部时钟的系统时钟和反馈时钟之间的相移。 电路包括差分脉冲发生器，当反馈时钟引导系统时钟时，差分脉冲发生器提供与反馈时钟180度异相的中间时钟，否则等于反馈时钟。 差分脉冲发生器还提供在一段时间内处于逻辑高的差分脉冲信号，通过该时间段，系统时钟和中间时钟的反相相移。 该电路还包括一个延迟控制单元和延迟单元，该延迟单元将临时时钟延迟一段时间。 所产生的与系统时钟相差180度的延迟中间时钟被反相，以提供与系统时钟同相的内部时钟。

公开(公告)号：US06642804B2

公开(公告)日：2003-11-04

申请号：US10074578

申请日：2002-02-13

申请人： Ioannis Chrissostomidis ,  Thoai-Thai Le

发明人： Ioannis Chrissostomidis ,  Thoai-Thai Le

IPC分类号： H03L700

CPC分类号： H03K3/0231 ,  H03K3/011

摘要： The invention creates an oscillator circuit, in particular for a refresh timer device of a dynamic semiconductor memory, having a capacitor device (C; C′) which is connected between a first node (6) and a first supply potential (P2); a current mirror circuit (T1; T2) for supplying a charging current for the capacitor device (C; C′) which is connected via a first transistor device (T4) to the first node (6) and which has a current source (SQ) for supplying a substantially temperature-independent reference current (Iref); a second transistor device (T5), which is connected between the first node (6) and the first supply potential (P2); the first and second transistor devices (T4; T5) and a control signal being configured in such a way that the capacitor device (C; C′) can be charged via the first node (6) when a potential (Vcomp) at the first node (6) is lower than the reference potential (Vref), and can be discharged via the first node (6) when the potential (Vcomp) at the first node (6) is higher than the reference potential (Vref) such that the signal at an output (A) oscillates.

摘要翻译： 本发明创建了一种振荡器电路，特别是用于动态半导体存储器的刷新定时器装置，其具有连接在第一节点（6）和第一电源电位（P2）之间的电容器装置（C; C'）; 用于为经由第一晶体管器件（T4）连接到第一节点（6）并且具有电流源（SQ）的电容器器件（C; C'）提供充电电流的电流镜电路（T1; T2） ），用于提供基本上温度无关的参考电流（Iref）; 连接在第一节点（6）和第一电源电位（P2）之间的第二晶体管器件（T5）; 第一和第二晶体管器件（T4; T5）和控制信号被配置成使得当第一和第二晶体管器件（T4; T5）的电位（V comp） 节点（6）低于参考电位（Vref），并且当第一节点（6）处的电位（Vcomp）高于参考电位（Vref）时，可以经由第一节点（6）放电， 输出（A）的信号振荡。

公开(公告)号：US6125073A

公开(公告)日：2000-09-26

申请号：US391717

申请日：1999-09-08

申请人： Thoai-Thai Le ,  Jurgen Lindolf ,  Eckhard Brass ,  Martin Brox

发明人： Thoai-Thai Le ,  Jurgen Lindolf ,  Eckhard Brass ,  Martin Brox

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C8/08 ,  G11C11/401 ,  G11C8/00

CPC分类号： G11C5/14 ,  G11C8/08

摘要： In an integrated semiconductor memory having a memory cell array divided into memory banks, supply potentials with high drive capability are applied to the memory banks only if the respective memory bank is activated for access to a memory cell. For this purpose a supply voltage assigned to the respective memory bank is controlled by the same address signal as the memory bank. The supply voltage sources generate a word line potential, a bit line potential or a substrate potential. As a result, a power loss is reduced.

摘要翻译： 在具有划分为存储体的存储单元阵列的集成半导体存储器中，只有当相应的存储体被激活以访问存储单元时，具有高驱动能力的电源才被施加到存储体。 为此，分配给相应存储体的电源电压由与存储体相同的地址信号控制。 电源电压源产生字线电位，位线电位或衬底电位。 结果，功率损耗降低。