公开(公告)号：US06444544B1

公开(公告)日：2002-09-03

申请号：US09629940

申请日：2000-08-01

申请人： Chu-Wei Hu ,  Chung-Te Lin ,  Kuo-Hua Pan ,  Hsien-Chin Lin

发明人： Chu-Wei Hu ,  Chung-Te Lin ,  Kuo-Hua Pan ,  Hsien-Chin Lin

IPC分类号： H01L21326

CPC分类号： H01L23/5258 ,  H01L23/53228 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming aluminum guard structures in copper interconnect structures, used to protect the copper interconnect structures from a laser write procedure, performed to an adjacent copper fuse element, has been developed. The method features forming guard structure openings in an upper level of the copper interconnect structures, in a region adjacent to a copper fuse element. Deposition and patterning of an aluminum layer result in the formation of aluminum guard structures, located in the guard structure openings. The aluminum guard structures protect the copper interconnect structures from the oxidizing and corrosive effects of oxygen, fluorine and water ions, which are generated during a laser write procedure, performed to the adjacent copper fuse element.

摘要翻译： 已经开发了一种在铜互连结构中形成用于保护铜互连结构免受激光写入过程的铝保护结构的方法，该方法对相邻的铜熔丝元件执行。 该方法的特征是在铜互连结构的上层形成保护结构开口，在铜熔丝元件的邻近区域。 铝层的沉积和图案化导致位于防护结构开口中的铝防护结构的形成。 铝保护结构保护铜互连结构免受在激光写入过程中产生的氧，氟和水离子对相邻铜熔丝元件的氧化和腐蚀作用。

公开(公告)号：US06362035B1

公开(公告)日：2002-03-26

申请号：US09498741

申请日：2000-02-07

申请人： Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Hsien-Chin Lin

发明人： Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Hsien-Chin Lin

IPC分类号： H01L2144

CPC分类号： H01L21/823878 ,  H01L21/76237 ,  Y10S438/919

摘要： A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. The channel stop implant follows planarization of the field oxide and is thereby essentially at the same depth in both field and active regions. Subsequently implanted p- and n-wells are formed deeper than the channel stop layer, the n-well implant being of a sufficiently higher dose to over compensate the channel stop layer, thereby removing it's effect from the n-well. A portion of the channel stop implant under the field oxide adjacent the p-well provides effective anti-punchthrough protection with only a small increase in junction capacitance. The method is shown for, and is particularly effective in, processes utilizing shallow trench isolation.

摘要翻译： 描述了一种用于在双阱CMOS工艺的场隔离下并入离子注入通道阻挡层的方法，其中该层通过在整个晶片上的覆盖硼离子注入直接放置在完成的场隔离下。 通道停止植入物遵循场氧化物的平坦化，并且因此在场和有源区域中基本上处于相同的深度。 随后，注入的p阱和n阱形成得比沟道阻挡层深，n阱注入量足够高的剂量，以过度补偿沟道阻挡层，从而从n阱中除去它的作用。 在p阱附近的场氧化物下的通道停止注入的一部分提供了有效的抗穿透保护，只有较小的结电容增加。 该方法在利用浅沟槽隔离的工艺中示出并且特别有效。

公开(公告)号：US20110127610A1

公开(公告)日：2011-06-02

申请号：US12797382

申请日：2010-06-09

申请人： Tung Ying Lee ,  Li-Wen Weng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Hsien-Chin Lin

发明人： Tung Ying Lee ,  Li-Wen Weng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Hsien-Chin Lin

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/66795 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785

摘要： A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

摘要翻译： 公开了一种用于制造多栅极半导体器件的系统和方法。 一个实施例包括多个散热片，其中散热片内隔离区域延伸到小于鳍间隔离区域的衬底内。 去除未被栅极堆叠覆盖的多个鳍片的区域，并且从衬底形成源极/漏极区域，以避免在源极/漏极区域中的鳍片之间形成空隙。

公开(公告)号：USRE40138E1

公开(公告)日：2008-03-04

申请号：US10442631

申请日：2003-05-21

申请人： Mu-Chi Chiang ,  Hsien-Chin Lin ,  Jiaw-Ren Shih

发明人： Mu-Chi Chiang ,  Hsien-Chin Lin ,  Jiaw-Ren Shih

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/6656

摘要： A process for fabricating input/output, N channel, (I/O NMOS) devices, featuring an ion implanted nitrogen region, used to reduce hot carrier electron, (HEC), injection, has been developed. The process features implanting a nitorgen region, at the interface of an overlying silicon oxide layer, and an underlying lightly doped source/drain, (LDD), region. The implantation procedure can either be performed prior to, or after, the deposition of a silicon oxide liner layer, in both cases resulting in a desired nitrogen pile-up at the oxide-LDD interface, as well as resulting, in a more graded LDD profile. An increase in the time to fail, in regards to HCE injection, for these I/O NMOS devices, is realized, when compared to counterparts fabricated without the nitrogen implantation procedure.

摘要翻译： 已经开发了用于制造用于减少热载流子电子（HEC）注入的具有离子注入氮区域的输入/输出N沟道（I / O NMOS）器件的工艺。 该过程的特征是在覆盖的氧化硅层的界面和下面的轻掺杂源极/漏极（LDD）区域上注入nitorgen区域。 在两种情况下，在氧化硅衬垫层的沉积之前或之后，可以进行注入工艺，导致在氧化物 - LDD界面处产生所需的氮堆积，以及在较梯度的LDD 个人资料 当与没有氮气注入程序制造的对手相比时，实现了对于这些I / O NMOS器件，关于HCE注入的失败时间的增加。

公开(公告)号：US06380021B1

公开(公告)日：2002-04-30

申请号：US09597193

申请日：2000-06-20

申请人： Jyh-Haur Wang ,  Chih-Chiang Wang ,  Hsien-Chin Lin ,  Kuo-Hua Pan ,  Carlos H. Diaz

发明人： Jyh-Haur Wang ,  Chih-Chiang Wang ,  Hsien-Chin Lin ,  Kuo-Hua Pan ,  Carlos H. Diaz

IPC分类号： H01L218238

CPC分类号： H01L21/823814

摘要： A new method for forming ultra-shallow junctions for PMOSFET while reducing short channel effects is described. A semiconductor substrate wafer is provided wherein there is at least one NMOS active area and at least one PMOS active area. Gate electrodes are formed in both the NMOS and PMOS areas. N-type source/drain extensions are implanted into the NMOS area. The wafer is annealed whereby the n-type source/drain extensions are driven in. Thereafter, p-type source/drain extensions are implanted in the PMOS area wherein the p-type source/drain extensions are not subjected to an annealing step. Spacers are formed on sidewalls of the NMOS and PMOS gate electrodes. Source/drain regions are implanted into the NMOS and PMOS areas wherein the source/drain regions are self-aligned to the spacers to complete formation of an integrated circuit device.

摘要翻译： 描述了一种用于在减少短沟道效应的同时形成PMOSFET的超浅结的新方法。 提供半导体衬底晶片，其中存在至少一个NMOS有源区和至少一个PMOS有效区。 栅电极形成在NMOS和PMOS区域中。 将N型源极/漏极延伸部分注入NMOS区域。 将晶片退火，由此驱动n型源极/漏极延伸部分。此后，在PMOS区域中注入p型源极/漏极延伸部分，其中p型源极/漏极延伸部未经历退火步骤。 间隔件形成在NMOS和PMOS栅电极的侧壁上。 源极/漏极区域被注入NMOS和PMOS区域，其中源极/漏极区域与间隔物自对准以完成集成电路器件的形成。

公开(公告)号：US5281492A

公开(公告)日：1994-01-25

申请号：US54603

申请日：1993-04-29

申请人： Hsien-Chin Lin

发明人： Hsien-Chin Lin

IPC分类号： H01M2/04 ,  H01M2/12

CPC分类号： H01M2/1217 ,  H01M2/043

摘要： A cover device for a storage battery includes a sub-cover that includes a flat bottom with a plurality of first vent-holes, a top portion and a connecting wall which interconnects the flat bottom and the top portion to define a space therein. The cover device further includes a plurality of tubes, each of which having n open end which is connected to each of the first vent-holes of the flat bottom and a closed end which is plugged into a respective inlet-hole of a main cover of the storage battery so as to close the inlet-hole, and a second vent-hole which is formed in the sub-cover and which communicates the space in the sub-cover with an exterior of the same.

摘要翻译： 一种用于蓄电池的盖装置包括：副盖，其包括具有多个第一通气孔的平底部，顶部和连接壁，其将平底部和顶部部分互连以限定其中的空间。 盖装置还包括多个管，每个管具有连接到平底部的每个第一通气孔的n个开口端，并且封闭端被插入主盖的相应入口孔中 所述蓄电池用于封闭所述入口孔;以及第二通气孔，其形成在所述副罩中并将所述副罩中的空间与所述副罩的外部连通。

公开(公告)号：US08426923B2

公开(公告)日：2013-04-23

申请号：US12797382

申请日：2010-06-09

申请人： Tung Ying Lee ,  Li-Wen Weng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Hsien-Chin Lin

发明人： Tung Ying Lee ,  Li-Wen Weng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Hsien-Chin Lin

IPC分类号： H01L29/423

CPC分类号： H01L29/66795 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785

摘要： A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

摘要翻译： 公开了一种用于制造多栅极半导体器件的系统和方法。 一个实施例包括多个散热片，其中散热片内隔离区域延伸到小于鳍间隔离区域的衬底内。 去除未被栅极堆叠覆盖的多个鳍片的区域，并且从衬底形成源极/漏极区域，以避免在源极/漏极区域中的鳍片之间形成空隙。

公开(公告)号：US06235600B1

公开(公告)日：2001-05-22

申请号：US09531403

申请日：2000-03-20

申请人： Mu-Chi Chiang ,  Hsien-Chin Lin ,  Jiaw-Ren Shih

发明人： Mu-Chi Chiang ,  Hsien-Chin Lin ,  Jiaw-Ren Shih

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/6656

摘要： A process for fabricating input/output, N channel, (I/O NMOS) devices, featuring an ion implanted nitrogen region, used to reduce hot carrier electron, (HEC), injection, has been developed. The process features implanting a nitorgen region, at the interface of an overlying silicon oxide layer, and an underlying lightly doped source/drain, (LDD), region. The implantation procedure can either be performed prior to, or after, the deposition of a silicon oxide liner layer, in both cases resulting in a desired nitrogen pile-up at the oxide-LDD interface, as well as resulting, in a more graded LDD profile. An increase in the time to fail, in regards to HCE injection, for these I/O NMOS devices, is realized, when compared to counterparts fabricated without the nitrogen implantation procedure.

摘要翻译： 已经开发了用于制造用于减少热载流子电子（HEC）注入的具有离子注入氮区域的输入/输出N沟道（I / O NMOS）器件的工艺。 该过程的特征是在覆盖的氧化硅层的界面和下面的轻掺杂源极/漏极（LDD）区域上注入nitorgen区域。 在两种情况下，在氧化硅衬垫层的沉积之前或之后，可以进行注入工艺，导致在氧化物 - LDD界面处产生所需的氮堆积，以及在较梯度的LDD 个人资料 当与没有氮气注入程序制造的对手相比时，实现了对于这些I / O NMOS器件，关于HCE注入的失败时间的增加。