公开(公告)号：US07754571B2

公开(公告)日：2010-07-13

申请号：US11592204

申请日：2006-11-03

Applicant: Ken Liao ,  Kuo-Hua Pan ,  Yun-Hsiu Chen ,  Syun-Ming Jang ,  Yi-Ching Lin

Inventor： Ken Liao ,  Kuo-Hua Pan ,  Yun-Hsiu Chen ,  Syun-Ming Jang ,  Yi-Ching Lin

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636

Abstract: A method for forming a strained channel in a semiconductor device is provided, comprises providing of a transistor comprising a gate stack exposed with a gate electrode on a semiconductor substrate, a pair of source/drain regions in the substrate on opposite sides of the gate stack and a pair of spacers on opposing sidewalls of the gate stack. A passivation layer is formed to cover the gate electrode and spacers of the transistor. A passivation layer is formed to cover the gate electrode and the spacers. A recess region is formed in each of the source/drain regions, wherein an edge of the recess region aligns to an outer edge of the spacers. The recess regions are filled with a strain-exerting material, thereby forming a strained channel region in the semiconductor substrate between the source/drain regions.

Abstract translation: 提供了一种在半导体器件中形成应变通道的方法，包括提供晶体管，该晶体管包括在半导体衬底上暴露有栅电极的栅极叠层，在栅极叠层的相对侧上的衬底中的一对源极/漏极区域 以及在栅极堆叠的相对的侧壁上的一对隔板。 形成钝化层以覆盖晶体管的栅电极和间隔物。 形成钝化层以覆盖栅电极和间隔物。 在每个源极/漏极区域中形成凹陷区域，其中凹部区域的边缘与间隔物的外边缘对准。 用应变施加材料填充凹陷区域，从而在源极/漏极区域之间的半导体衬底中形成应变通道区域。

公开(公告)号：US06444544B1

公开(公告)日：2002-09-03

申请号：US09629940

申请日：2000-08-01

Applicant: Chu-Wei Hu ,  Chung-Te Lin ,  Kuo-Hua Pan ,  Hsien-Chin Lin

Inventor： Chu-Wei Hu ,  Chung-Te Lin ,  Kuo-Hua Pan ,  Hsien-Chin Lin

IPC: H01L21326

CPC classification number: H01L23/5258 ,  H01L23/53228 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming aluminum guard structures in copper interconnect structures, used to protect the copper interconnect structures from a laser write procedure, performed to an adjacent copper fuse element, has been developed. The method features forming guard structure openings in an upper level of the copper interconnect structures, in a region adjacent to a copper fuse element. Deposition and patterning of an aluminum layer result in the formation of aluminum guard structures, located in the guard structure openings. The aluminum guard structures protect the copper interconnect structures from the oxidizing and corrosive effects of oxygen, fluorine and water ions, which are generated during a laser write procedure, performed to the adjacent copper fuse element.

Abstract translation: 已经开发了一种在铜互连结构中形成用于保护铜互连结构免受激光写入过程的铝保护结构的方法，该方法对相邻的铜熔丝元件执行。 该方法的特征是在铜互连结构的上层形成保护结构开口，在铜熔丝元件的邻近区域。 铝层的沉积和图案化导致位于防护结构开口中的铝防护结构的形成。 铝保护结构保护铜互连结构免受在激光写入过程中产生的氧，氟和水离子对相邻铜熔丝元件的氧化和腐蚀作用。

公开(公告)号：US6074905A

公开(公告)日：2000-06-13

申请号：US222285

申请日：1998-12-28

Applicant: Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Shan Hou ,  Kuo-Hua Pan

Inventor： Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Shan Hou ,  Kuo-Hua Pan

IPC: H01L21/311 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/66575 ,  H01L21/31111 ,  H01L21/823835 ,  H01L29/665

Abstract: A new method for forming polysilicon lines using a SiON anti-reflective coating during photolithography wherein a thin oxide protection layer is formed over the polysilicon sidewalls and active area surfaces after etching to prevent damage caused by removal of the SiON in the fabrication of integrated circuits is achieved. A gate oxide layer is provided on the surface of a silicon substrate. A polysilicon layer is deposited overlying the gate oxide layer. A SiON anti-reflective coating layer is deposited overlying the polysilicon layer. A photoresist mask is formed over the SiON anti-reflective coating layer. The SiON anti-reflective coating layer, polysilicon layer, and gate oxide layer are etched away where they are not covered by the photoresist mask to form polysilicon lines. The polysilicon lines and the silicon substrate are oxidized to form a protective oxide layer on the sidewalls of the polysilicon lines and on the surface of the silicon substrate. The SiON anti-reflective coating layer is removed wherein the protective oxide layer protects the polysilicon lines and the silicon substrate from damage to complete fabrication of polysilicon lines in the manufacture of an integrated circuit device.

Abstract translation: 在光刻期间使用SiON抗反射涂层形成多晶硅线的新方法，其中在蚀刻之后在多晶硅侧壁和有源区表面上形成薄氧化物保护层以防止在集成电路的制造中由于SiON的去除而引起的损坏。 实现了 在硅衬底的表面上设置栅氧化层。 沉积在栅极氧化物层上的多晶硅层。 在多晶硅层上沉积SiON抗反射涂层。 在SiON抗反射涂层上形成光致抗蚀剂掩模。 SiON抗反射涂层，多晶硅层和栅极氧化物层被蚀刻掉，其中它们不被光致抗蚀剂掩模覆盖以形成多晶硅线。 多晶硅线路和硅衬底被氧化以在多晶硅线路的侧壁和硅衬底的表面上形成保护氧化物层。 去除SiON抗反射涂层，其中保护性氧化物层保护多晶硅线和硅衬底免于在集成电路器件的制造中完全制造多晶硅线。

公开(公告)号：US20120206953A1

公开(公告)日：2012-08-16

申请号：US13025872

申请日：2011-02-11

Applicant: Hong-Chen CHENG ,  Ming-Yi LEE ,  Kuo-Hua PAN ,  Jung-Hsuan CHEN ,  Li-Chun TIEN ,  Cheng Hung LEE ,  Hung-Jen LIAO

Inventor： Hong-Chen CHENG ,  Ming-Yi LEE ,  Kuo-Hua PAN ,  Jung-Hsuan CHEN ,  Li-Chun TIEN ,  Cheng Hung LEE ,  Hung-Jen LIAO

IPC: G11C5/06 ,  H01L25/00

CPC classification number: G11C5/06 ,  G11C5/147 ,  G11C5/148 ,  G11C11/417

Abstract: A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.

Abstract translation: 电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。 第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。

公开(公告)号：US07816686B2

公开(公告)日：2010-10-19

申请号：US11811694

申请日：2007-06-12

Applicant: Kuo-Hua Pan ,  Ken Liao ,  Augus Tai ,  Harry Chuang

Inventor： Kuo-Hua Pan ,  Ken Liao ,  Augus Tai ,  Harry Chuang

IPC: H01L29/00

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/76895 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

Abstract: A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; an epitaxial region having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the epitaxial region comprises an impurity of a first conductivity type; a first portion of the semiconductor substrate adjoining the epitaxial region, wherein the first portion of the semiconductor substrate is of the first conductivity type; and a second portion of the semiconductor substrate adjoining the first portion. The second portion of the semiconductor substrate is of a second conductivity type opposite the first conductivity type. A silicide region is formed on the epitaxial region and the first and the second portions of the semiconductor substrate.

Abstract translation: 半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; 外延区域，其具有半导体衬底中的至少一部分并且与栅叠层相邻，其中所述外延区域包括第一导电类型的杂质; 所述半导体衬底的与所述外延区相邻的第一部分，其中所述半导体衬底的所述第一部分是所述第一导电类型; 以及与所述第一部分相邻的所述半导体基板的第二部分。 半导体衬底的第二部分是与第一导电类型相反的第二导电类型。 在外延区域和半导体衬底的第一和第二部分上形成硅化物区域。

公开(公告)号：US20080308842A1

公开(公告)日：2008-12-18

申请号：US11811694

申请日：2007-06-12

Applicant: Kuo-Hua Pan ,  Ken Liao ,  Augus Tai ,  Harry Chuang

Inventor： Kuo-Hua Pan ,  Ken Liao ,  Augus Tai ,  Harry Chuang

IPC: H01L29/778

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/76895 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

Abstract: A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; an epitaxial region having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the epitaxial region comprises an impurity of a first conductivity type; a first portion of the semiconductor substrate adjoining the epitaxial region, wherein the first portion of the semiconductor substrate is of the first conductivity type; and a second portion of the semiconductor substrate adjoining the first portion. The second portion of the semiconductor substrate is of a second conductivity type opposite the first conductivity type. A silicide region is formed on the epitaxial region and the first and the second portions of the semiconductor substrate.

Abstract translation: 半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; 外延区域，其具有半导体衬底中的至少一部分并且与栅叠层相邻，其中所述外延区域包括第一导电类型的杂质; 所述半导体衬底的与所述外延区相邻的第一部分，其中所述半导体衬底的所述第一部分是所述第一导电类型; 以及与所述第一部分相邻的所述半导体基板的第二部分。 半导体衬底的第二部分是与第一导电类型相反的第二导电类型。 在外延区域和半导体衬底的第一和第二部分上形成硅化物区域。

公开(公告)号：US20080124875A1

公开(公告)日：2008-05-29

申请号：US11592204

申请日：2006-11-03

Applicant: Ken Liao ,  Kuo-Hua Pan ,  Yun-Hsiu Chen ,  Syun-Ming Jang ,  Yi-Ching Lin

Inventor： Ken Liao ,  Kuo-Hua Pan ,  Yun-Hsiu Chen ,  Syun-Ming Jang ,  Yi-Ching Lin

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636

Abstract: A method for forming a strained channel in a semiconductor device is provided, comprises providing of a transistor comprising a gate stack exposed with a gate electrode on a semiconductor substrate, a pair of source/drain regions in the substrate on opposite sides of the gate stack and a pair of spacers on opposing sidewalls of the gate stack. A passivation layer is formed to cover the gate electrode and spacers of the transistor. A passivation layer is formed to cover the gate electrode and the spacers. A recess region is formed in each of the source/drain regions, wherein an edge of the recess region aligns to an outer edge of the spacers. The recess regions are filled with a strain-exerting material, thereby forming a strained channel region in the semiconductor substrate between the source/drain regions.

Abstract translation: 提供了一种在半导体器件中形成应变通道的方法，包括提供晶体管，其包括在半导体衬底上暴露有栅极电极的栅极堆叠，在栅极堆叠的相对侧的衬底中的一对源极/漏极区域 以及在栅极堆叠的相对的侧壁上的一对隔板。 形成钝化层以覆盖晶体管的栅电极和间隔物。 形成钝化层以覆盖栅电极和间隔物。 在每个源极/漏极区域中形成凹陷区域，其中凹部区域的边缘与间隔物的外边缘对准。 用应变施加材料填充凹陷区域，从而在源极/漏极区域之间的半导体衬底中形成应变通道区域。

公开(公告)号：US06207538B1

公开(公告)日：2001-03-27

申请号：US09472998

申请日：1999-12-28

Applicant: Kuo-Hua Pan ,  Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Hsiung Ho

Inventor： Kuo-Hua Pan ,  Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Hsiung Ho

IPC: H01L2104

CPC classification number: H01L21/823892

Abstract: A method for forming both n and p wells in a semiconductor substrate using a single photolithography masking step, a non-conformal oxide layer and a chemical-mechanical polish step. A screen oxide layer is formed on a semiconductor substrate. A barrier layer is formed on the screen oxide layer. The barrier layer is patterned to form a first opening in the barrier layer over regions of the substrate where first wells will be formed. We implant impurities of a first conductivity type into the substrate to form first wells. In a key step, a non-conformal oxide layer is formed over the first well regions and the barrier layer. It is critical that the non-conformal oxide layer formed using a HDPCVD process. The non-conformal oxide layer is chemical-mechanical polished stopping at the barrier layer. The barrier layer is removed using a selective etch, to form second openings in the remaining non-conformal oxide layer over areas where second well will be formed in the substrate. Using the remaining non-conformal oxide as a mask, we implant impurities of the second conductivity type through the second openings to form second wells. The remaining non-conformal oxide layer and the screen oxide layer are removed.

Abstract translation: 一种使用单一光刻掩模步骤，非保形氧化物层和化学机械抛光步骤在半导体衬底中形成n阱和p阱的方法。 在半导体基板上形成荧光体层。 在屏幕氧化物层上形成阻挡层。 阻挡层被图案化以在衬底的形成第一阱的区域上的阻挡层中形成第一开口。 我们将第一导电类型的杂质植入衬底中以形成第一孔。 在关键步骤中，在第一阱区和阻挡层上形成非共形氧化物层。 使用HDPCVD工艺形成的非共形氧化物层是至关重要的。 非保形氧化物层在阻挡层处被化学机械抛光停止。 使用选择性蚀刻去除阻挡层，以在剩余的非保形氧化物层中在衬底中将形成第二阱的区域上形成第二开口。 使用剩余的非保形氧化物作为掩模，我们通过第二开口植入第二导电类型的杂质以形成第二孔。 去除剩余的非保形氧化物层和屏幕氧化物层。

公开(公告)号：US08482990B2

公开(公告)日：2013-07-09

申请号：US13025872

申请日：2011-02-11

Applicant: Hong-Chen Cheng ,  Ming-Yi Lee ,  Kuo-Hua Pan ,  Jung-Hsuan Chen ,  Li-Chun Tien ,  Cheng Hung Lee ,  Hung-Jen Liao

Inventor： Hong-Chen Cheng ,  Ming-Yi Lee ,  Kuo-Hua Pan ,  Jung-Hsuan Chen ,  Li-Chun Tien ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC: G11C7/10

CPC classification number: G11C5/06 ,  G11C5/147 ,  G11C5/148 ,  G11C11/417

Abstract: A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.

Abstract translation: 电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。 第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。

公开(公告)号：US06380021B1

公开(公告)日：2002-04-30

申请号：US09597193

申请日：2000-06-20

Applicant: Jyh-Haur Wang ,  Chih-Chiang Wang ,  Hsien-Chin Lin ,  Kuo-Hua Pan ,  Carlos H. Diaz

Inventor： Jyh-Haur Wang ,  Chih-Chiang Wang ,  Hsien-Chin Lin ,  Kuo-Hua Pan ,  Carlos H. Diaz

IPC: H01L218238

CPC classification number: H01L21/823814

Abstract: A new method for forming ultra-shallow junctions for PMOSFET while reducing short channel effects is described. A semiconductor substrate wafer is provided wherein there is at least one NMOS active area and at least one PMOS active area. Gate electrodes are formed in both the NMOS and PMOS areas. N-type source/drain extensions are implanted into the NMOS area. The wafer is annealed whereby the n-type source/drain extensions are driven in. Thereafter, p-type source/drain extensions are implanted in the PMOS area wherein the p-type source/drain extensions are not subjected to an annealing step. Spacers are formed on sidewalls of the NMOS and PMOS gate electrodes. Source/drain regions are implanted into the NMOS and PMOS areas wherein the source/drain regions are self-aligned to the spacers to complete formation of an integrated circuit device.

Abstract translation: 描述了一种用于在减少短沟道效应的同时形成PMOSFET的超浅结的新方法。 提供半导体衬底晶片，其中存在至少一个NMOS有源区和至少一个PMOS有效区。 栅电极形成在NMOS和PMOS区域中。 将N型源极/漏极延伸部分注入NMOS区域。 将晶片退火，由此驱动n型源极/漏极延伸部分。此后，在PMOS区域中注入p型源极/漏极延伸部分，其中p型源极/漏极延伸部未经历退火步骤。 间隔件形成在NMOS和PMOS栅电极的侧壁上。 源极/漏极区域被注入NMOS和PMOS区域，其中源极/漏极区域与间隔物自对准以完成集成电路器件的形成。