公开(公告)号：US06444544B1

公开(公告)日：2002-09-03

申请号：US09629940

申请日：2000-08-01

申请人： Chu-Wei Hu ,  Chung-Te Lin ,  Kuo-Hua Pan ,  Hsien-Chin Lin

发明人： Chu-Wei Hu ,  Chung-Te Lin ,  Kuo-Hua Pan ,  Hsien-Chin Lin

IPC分类号： H01L21326

CPC分类号： H01L23/5258 ,  H01L23/53228 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming aluminum guard structures in copper interconnect structures, used to protect the copper interconnect structures from a laser write procedure, performed to an adjacent copper fuse element, has been developed. The method features forming guard structure openings in an upper level of the copper interconnect structures, in a region adjacent to a copper fuse element. Deposition and patterning of an aluminum layer result in the formation of aluminum guard structures, located in the guard structure openings. The aluminum guard structures protect the copper interconnect structures from the oxidizing and corrosive effects of oxygen, fluorine and water ions, which are generated during a laser write procedure, performed to the adjacent copper fuse element.

摘要翻译： 已经开发了一种在铜互连结构中形成用于保护铜互连结构免受激光写入过程的铝保护结构的方法，该方法对相邻的铜熔丝元件执行。 该方法的特征是在铜互连结构的上层形成保护结构开口，在铜熔丝元件的邻近区域。 铝层的沉积和图案化导致位于防护结构开口中的铝防护结构的形成。 铝保护结构保护铜互连结构免受在激光写入过程中产生的氧，氟和水离子对相邻铜熔丝元件的氧化和腐蚀作用。

公开(公告)号：US6074905A

公开(公告)日：2000-06-13

申请号：US222285

申请日：1998-12-28

申请人： Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Shan Hou ,  Kuo-Hua Pan

发明人： Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Shan Hou ,  Kuo-Hua Pan

IPC分类号： H01L21/311 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/66575 ,  H01L21/31111 ,  H01L21/823835 ,  H01L29/665

摘要： A new method for forming polysilicon lines using a SiON anti-reflective coating during photolithography wherein a thin oxide protection layer is formed over the polysilicon sidewalls and active area surfaces after etching to prevent damage caused by removal of the SiON in the fabrication of integrated circuits is achieved. A gate oxide layer is provided on the surface of a silicon substrate. A polysilicon layer is deposited overlying the gate oxide layer. A SiON anti-reflective coating layer is deposited overlying the polysilicon layer. A photoresist mask is formed over the SiON anti-reflective coating layer. The SiON anti-reflective coating layer, polysilicon layer, and gate oxide layer are etched away where they are not covered by the photoresist mask to form polysilicon lines. The polysilicon lines and the silicon substrate are oxidized to form a protective oxide layer on the sidewalls of the polysilicon lines and on the surface of the silicon substrate. The SiON anti-reflective coating layer is removed wherein the protective oxide layer protects the polysilicon lines and the silicon substrate from damage to complete fabrication of polysilicon lines in the manufacture of an integrated circuit device.

摘要翻译： 在光刻期间使用SiON抗反射涂层形成多晶硅线的新方法，其中在蚀刻之后在多晶硅侧壁和有源区表面上形成薄氧化物保护层以防止在集成电路的制造中由于SiON的去除而引起的损坏。 实现了 在硅衬底的表面上设置栅氧化层。 沉积在栅极氧化物层上的多晶硅层。 在多晶硅层上沉积SiON抗反射涂层。 在SiON抗反射涂层上形成光致抗蚀剂掩模。 SiON抗反射涂层，多晶硅层和栅极氧化物层被蚀刻掉，其中它们不被光致抗蚀剂掩模覆盖以形成多晶硅线。 多晶硅线路和硅衬底被氧化以在多晶硅线路的侧壁和硅衬底的表面上形成保护氧化物层。 去除SiON抗反射涂层，其中保护性氧化物层保护多晶硅线和硅衬底免于在集成电路器件的制造中完全制造多晶硅线。

公开(公告)号：US06207538B1

公开(公告)日：2001-03-27

申请号：US09472998

申请日：1999-12-28

申请人： Kuo-Hua Pan ,  Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Hsiung Ho

发明人： Kuo-Hua Pan ,  Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Hsiung Ho

IPC分类号： H01L2104

CPC分类号： H01L21/823892

摘要： A method for forming both n and p wells in a semiconductor substrate using a single photolithography masking step, a non-conformal oxide layer and a chemical-mechanical polish step. A screen oxide layer is formed on a semiconductor substrate. A barrier layer is formed on the screen oxide layer. The barrier layer is patterned to form a first opening in the barrier layer over regions of the substrate where first wells will be formed. We implant impurities of a first conductivity type into the substrate to form first wells. In a key step, a non-conformal oxide layer is formed over the first well regions and the barrier layer. It is critical that the non-conformal oxide layer formed using a HDPCVD process. The non-conformal oxide layer is chemical-mechanical polished stopping at the barrier layer. The barrier layer is removed using a selective etch, to form second openings in the remaining non-conformal oxide layer over areas where second well will be formed in the substrate. Using the remaining non-conformal oxide as a mask, we implant impurities of the second conductivity type through the second openings to form second wells. The remaining non-conformal oxide layer and the screen oxide layer are removed.

摘要翻译： 一种使用单一光刻掩模步骤，非保形氧化物层和化学机械抛光步骤在半导体衬底中形成n阱和p阱的方法。 在半导体基板上形成荧光体层。 在屏幕氧化物层上形成阻挡层。 阻挡层被图案化以在衬底的形成第一阱的区域上的阻挡层中形成第一开口。 我们将第一导电类型的杂质植入衬底中以形成第一孔。 在关键步骤中，在第一阱区和阻挡层上形成非共形氧化物层。 使用HDPCVD工艺形成的非共形氧化物层是至关重要的。 非保形氧化物层在阻挡层处被化学机械抛光停止。 使用选择性蚀刻去除阻挡层，以在剩余的非保形氧化物层中在衬底中将形成第二阱的区域上形成第二开口。 使用剩余的非保形氧化物作为掩模，我们通过第二开口植入第二导电类型的杂质以形成第二孔。 去除剩余的非保形氧化物层和屏幕氧化物层。

公开(公告)号：US06583017B2

公开(公告)日：2003-06-24

申请号：US09927072

申请日：2001-08-10

申请人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

发明人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

摘要： A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

摘要翻译： 一种用于产生具有升高的源极/漏极区域的自对准沟道植入物的方法。 在硅衬底的顶部形成薄的电介质层，在该电介质上沉积厚层氧化物。 将开口暴露并蚀刻通过氧化物层，通过电介质并进入下面的硅衬底，在衬底中形成浅沟槽。 通过执行通道注入LDD注入，口袋注入，形成栅极间隔物和电极，移除厚层氧化物并形成S / D区域，栅极电极已经产生了升高的S / D区域。 通过形成栅极间隔物，进行沟道注入，形成栅电极，去除厚层氧化物并执行S / D注入，已经产生了具有升高的S / D区域和一次性间隔物的栅电极。 通过形成栅极间隔物和栅电极，去除厚层氧化物并进行S / D注入，已经产生了具有升高的S / D区域和间隔物的栅电极，其中栅极聚合物突出在间隔物上方，从而增强了硅化物的形成 。

公开(公告)号：US06287926B1

公开(公告)日：2001-09-11

申请号：US09253297

申请日：1999-02-19

申请人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

发明人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

摘要： A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

摘要翻译： 一种用于产生具有升高的源极/漏极区域的自对准沟道植入物的方法。 在硅衬底的顶部形成薄的电介质层，在该电介质上沉积厚层氧化物。 将开口暴露并蚀刻通过氧化物层，通过电介质并进入下面的硅衬底，在衬底中形成浅沟槽。 通过执行通道注入LDD注入，口袋注入，形成栅极间隔物和电极，移除厚层氧化物并形成S / D区域，栅极电极已经产生了升高的S / D区域。 通过形成栅极间隔物，进行沟道注入，形成栅电极，去除厚层氧化物并执行S / D注入，已经产生了具有升高的S / D区域和一次性间隔物的栅电极。 通过形成栅极间隔物和栅电极，去除厚层氧化物并进行S / D注入，已经产生了具有升高的S / D区域和间隔物的栅电极，其中栅极聚合物突出在间隔物上方，从而增强了硅化物的形成 。

公开(公告)号：US06790756B2

公开(公告)日：2004-09-14

申请号：US10385954

申请日：2003-03-11

申请人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So Wein Kuo

发明人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So Wein Kuo

IPC分类号： H01L213205

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

摘要： A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

摘要翻译： 一种用于产生具有升高的源极/漏极区域的自对准沟道植入物的方法。 在硅衬底的顶部形成薄的电介质层，在该电介质上沉积厚层氧化物。 将开口暴露并蚀刻通过氧化物层，通过电介质并进入下面的硅衬底，在衬底中形成浅沟槽。 通过执行通道注入LDD注入，口袋注入，形成栅极间隔物和电极，移除厚层氧化物并形成S / D区域，栅极电极已经产生了升高的S / D区域。 通过形成栅极间隔物，进行沟道注入，形成栅电极，去除厚层氧化物并执行S / D注入，已经产生了具有升高的S / D区域和一次性间隔物的栅电极。 通过形成栅极间隔物和栅电极，去除厚层氧化物并进行S / D注入，已经产生了具有升高的S / D区域和间隔物的栅电极，其中栅极聚合物突出在间隔物上方，从而增强了硅化物的形成 。

公开(公告)号：US08778717B2

公开(公告)日：2014-07-15

申请号：US12726215

申请日：2010-03-17

申请人： Ru-Shang Hsiao ,  Chung-Te Lin ,  Nai-Wen Cheng ,  Yin-Kai Liao ,  Wei Chuang Wu

发明人： Ru-Shang Hsiao ,  Chung-Te Lin ,  Nai-Wen Cheng ,  Yin-Kai Liao ,  Wei Chuang Wu

IPC分类号： H01L21/00

CPC分类号： H01L21/76213 ,  H01L21/26513 ,  H01L21/26533 ,  H01L31/103 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A method of forming an integrated circuit structure includes providing a silicon substrate, and implanting a p-type impurity into the silicon substrate to form a p-type region. After the step of implanting, performing an anneal to form a silicon oxide region, with a portion of the p-type region converted to the silicon oxide region.

摘要翻译： 形成集成电路结构的方法包括提供硅衬底，并将p型杂质注入硅衬底中以形成p型区域。 在注入步骤之后，进行退火以形成氧化硅区域，其中一部分p型区域转换为氧化硅区域。

公开(公告)号：US08158474B2

公开(公告)日：2012-04-17

申请号：US12873889

申请日：2010-09-01

申请人： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

发明人： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

IPC分类号： H01L21/0243 ,  H01L23/76

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.

摘要翻译： 提供具有局部应力源的诸如PMOS晶体管的半导体器件。 凹槽形成在栅电极的相对侧上，使得凹槽通过假间隔件从栅电极偏移。 这些凹部填充有应力诱导层。 去除虚拟凹槽并形成轻掺杂的排水沟。 此后，形成新的间隔物并且应力诱导层凹陷。 可以执行一个或多个附加植入物以完成源极/漏极区域。 在一个实施例中，PMOS晶体管可以形成在与一个或多个NMOS晶体管相同的衬底上。 也可以在PMOS和/或NMOS晶体管上形成双重蚀刻停止层。

公开(公告)号：US08051392B2

公开(公告)日：2011-11-01

申请号：US12212088

申请日：2008-09-17

申请人： Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

发明人： Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

IPC分类号： G06F17/50 ,  G06F7/66 ,  G06K9/00 ,  H01L21/66

摘要： A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a second logic operation to expand the first feature to a second region greater than the first region. The pattern of the second region may be used to form the masks.

公开(公告)号：US20080272410A1

公开(公告)日：2008-11-06

申请号：US11743519

申请日：2007-05-02

申请人： Chung-Te Lin

发明人： Chung-Te Lin

IPC分类号： H01L29/76

CPC分类号： H01L21/76897 ,  H01L21/76829 ,  H01L21/76831 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A metal-oxide-semiconductor field-effect transistor (MOSFET) having self-aligned spacer contacts is provided. In accordance with embodiments of the present invention, a transistor, having a gate electrode and source/drain regions formed on opposing sides of the gate electrode, is covered with a first dielectric layer. A first contact opening is formed in the first dielectric layer to expose at least a portion of one of the source/drain regions. A second dielectric layer is formed over the first dielectric layer. Thereafter, an inter-layer dielectric layer is formed over the second dielectric layer and a second contact opening is formed through the inter-layer dielectric layer. In an embodiment, an etch-back process may be performed on the second dielectric layer prior to forming the inter-layer dielectric layer.

摘要翻译： 提供了具有自对准间隔触点的金属氧化物半导体场效应晶体管（MOSFET）。 根据本发明的实施例，具有形成在栅电极的相对侧上的栅电极和源极/漏极区的晶体管被​​第一介电层覆盖。 在第一电介质层中形成第一接触开口以暴露源/漏区之一的至少一部分。 在第一电介质层上形成第二电介质层。 此后，在第二电介质层上形成层间电介质层，通过层间电介质层形成第二接触开口。 在一个实施例中，可以在形成层间电介质层之前在第二电介质层上执行回蚀工艺。