利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

13 条记录 (耗时 0.028 秒)

    Multiple-gate semiconductor device and method
    1.
    发明授权
    Multiple-gate semiconductor device and method 有权
    多栅半导体器件及方法

    公开(公告)号：US08426923B2

    公开(公告)日：2013-04-23

    申请号：US12797382

    申请日：2010-06-09

    申请人： Tung Ying Lee ,  Li-Wen Weng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Hsien-Chin Lin

    发明人： Tung Ying Lee ,  Li-Wen Weng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Hsien-Chin Lin

    IPC分类号： H01L29/423

    CPC分类号： H01L29/66795 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785

    摘要： A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

    摘要翻译： 公开了一种用于制造多栅极半导体器件的系统和方法。 一个实施例包括多个散热片，其中散热片内隔离区域延伸到小于鳍间隔离区域的衬底内。 去除未被栅极堆叠覆盖的多个鳍片的区域，并且从衬底形成源极/漏极区域，以避免在源极/漏极区域中的鳍片之间形成空隙。

    Multiple-Gate Semiconductor Device and Method
    2.
    发明申请
    Multiple-Gate Semiconductor Device and Method 有权
    多栅极半导体器件及方法

    公开(公告)号：US20110127610A1

    公开(公告)日：2011-06-02

    申请号：US12797382

    申请日：2010-06-09

    申请人： Tung Ying Lee ,  Li-Wen Weng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Hsien-Chin Lin

    发明人： Tung Ying Lee ,  Li-Wen Weng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Hsien-Chin Lin

    IPC分类号： H01L27/088 ,  H01L21/8234

    CPC分类号： H01L29/66795 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785

    摘要： A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

    摘要翻译： 公开了一种用于制造多栅极半导体器件的系统和方法。 一个实施例包括多个散热片，其中散热片内隔离区域延伸到小于鳍间隔离区域的衬底内。 去除未被栅极堆叠覆盖的多个鳍片的区域，并且从衬底形成源极/漏极区域，以避免在源极/漏极区域中的鳍片之间形成空隙。

    Method of making a finFET, and finFET formed by the method
    6.
    发明授权
    Method of making a finFET, and finFET formed by the method 有权
    制造finFET的方法和通过该方法形成的finFET

    公开(公告)号：US09312179B2

    公开(公告)日：2016-04-12

    申请号：US12725554

    申请日：2010-03-17

    申请人： Chia-Pin Lin ,  Chien-Tai Chan ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

    发明人： Chia-Pin Lin ,  Chien-Tai Chan ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

    IPC分类号： H01L27/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

    CPC分类号： H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

    摘要： A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.

    摘要翻译： 一种方法包括形成在半导体衬底之上延伸的finFET的第一和第二鳍片，其间具有浅沟槽隔离（STI）区域，以及STI区域的顶表面与第一鳍片和第二鳍片的顶表面之间的距离。 第一和第二鳍片延伸部分设置在STI区域顶表面上方的第一和第二鳍片的顶表面和侧表面上。 从STI区域去除材料，以增加STI区域的顶表面与第一和第二鳍片的顶表面之间的距离。 保形应力源电介质材料沉积在鳍片和STI区域上。 共形介电应力材料被回流，以流入STI区域的顶表面之上的第一和第二鳍片之间的空间，以向finFET的沟道施加应力。

    Techniques for FinFET doping
    7.
    发明授权
    Techniques for FinFET doping 有权
    FinFET掺杂技术

    公开(公告)号：US08785286B2

    公开(公告)日：2014-07-22

    申请号：US12702803

    申请日：2010-02-09

    申请人： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Mao-Rong Yeh ,  Da-Wen Lin

    发明人： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Mao-Rong Yeh ,  Da-Wen Lin

    IPC分类号： H01L21/336 ,  H01L21/26 ,  H01L21/42 ,  H01L21/223

    CPC分类号： H01L29/66803 ,  H01L21/2236 ,  H01L21/2254 ,  H01L21/26526 ,  H01L21/26586

    摘要： A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.

    摘要翻译： 一种形成集成电路的方法包括提供半导体晶片，该半导体晶片包括在半导体晶片的表面上分配的半导体鳍; 在所述半导体鳍片的顶表面和侧壁上形成具有杂质的富掺杂层，其中所述杂质为n型或p型; 执行敲击植入以将杂质驱动到半导体鳍片中; 并除去富含掺杂剂的层。

    Techniques for FinFET Doping
    8.
    发明申请
    Techniques for FinFET Doping 有权
    FinFET掺杂技术

    公开(公告)号：US20110195555A1

    公开(公告)日：2011-08-11

    申请号：US12702803

    申请日：2010-02-09

    申请人： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Mao-Rong Yeh ,  Da-Wen Lin

    发明人： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Mao-Rong Yeh ,  Da-Wen Lin

    IPC分类号： H01L21/336 ,  H01L21/265

    CPC分类号： H01L29/66803 ,  H01L21/2236 ,  H01L21/2254 ,  H01L21/26526 ,  H01L21/26586

    摘要： A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.

    摘要翻译： 一种形成集成电路的方法包括提供半导体晶片，该半导体晶片包括在半导体晶片的表面上分配的半导体鳍; 在所述半导体鳍片的顶表面和侧壁上形成具有杂质的富掺杂层，其中所述杂质为n型或p型; 执行敲击植入以将杂质驱动到半导体鳍片中; 并除去富含掺杂剂的层。

    Method for obtaining quality ultra-shallow doped regions and device having same
    9.
    发明授权
    Method for obtaining quality ultra-shallow doped regions and device having same 有权
    用于获得优质超浅掺杂区域的方法及其装置

    公开(公告)号：US07994016B2

    公开(公告)日：2011-08-09

    申请号：US12616406

    申请日：2009-11-11

    申请人： Chun-Hsiung Tsai ,  Chun-Feng Nieh ,  Da-Wen Lin ,  Chien-Tai Chan

    发明人： Chun-Hsiung Tsai ,  Chun-Feng Nieh ,  Da-Wen Lin ,  Chien-Tai Chan

    IPC分类号： H01L21/336

    CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming ultra-shallow p-type lightly doped drain (LDD) regions of a PMOS transistor in a surface of a substrate includes the steps of providing a gaseous mixture of an inert gas, a boron-containing source, and an optional carbon-containing source, wherein the concentration of the gaseous mixture is at least 99.5% dilute with the inert gas and the optional carbon-containing source, if present, forming the gaseous mixture into a plasma, and forming the LDD regions, wherein the forming step includes plasma-doping the boron into the substrate using the plasma. N-type pocket regions are formed in the substrate underneath and adjacent to the LDD regions, wherein for a PMOS transistor having a threshold voltage of 100 mV, the n-type pocket regions include phosphorous impurities at a dopant concentration of less than 6.0×1018 atoms/cm3 or a proportionately lower/higher dopant concentration for a lower/higher threshold voltage.

    摘要翻译： 在衬底的表面中形成PMOS晶体管的超浅p型轻掺杂漏极（LDD）区域的方法包括以下步骤：提供惰性气体，含硼源和任选的碳的气态混合物 其中气态混合物的浓度与惰性气体和任选的含碳源（如果存在）一起稀释至少99.5％，将气态混合物形成等离子体，并形成LDD区域，其中形成步骤 包括使用等离子体将硼等离子体掺杂到衬底中。 在LDD区域下方并与LDD区域相邻的衬底中形成N型口袋区域，其中对于阈值电压为100mV的PMOS晶体管，n型袋区域包括掺杂剂浓度小于6.0×1018的磷杂质 原子/ cm 3或低/高阈值电压的比例较低/较高掺杂剂浓度。

    Integrated circuits
    10.
    发明授权
    Integrated circuits 有权
    集成电路

    公开(公告)号：US08884341B2

    公开(公告)日：2014-11-11

    申请号：US13210962

    申请日：2011-08-16

    申请人： Chun Hsiung Tsai ,  Su-Hao Liu ,  Chien-Tai Chan ,  King-Yuen Wong ,  Chien-Chang Su

    发明人： Chun Hsiung Tsai ,  Su-Hao Liu ,  Chien-Tai Chan ,  King-Yuen Wong ,  Chien-Chang Su

    IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L29/08

    CPC分类号： H01L29/7834 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/6653 ,  H01L29/66636

    摘要： An integrated circuit includes a gate electrode disposed over a substrate. A source/drain (S/D) region is disposed adjacent to the gate electrode. The S/D region includes a diffusion barrier structure disposed in a recess of the substrate. The diffusion barrier structure includes a first portion and a second portion. The first portion is adjacent to the gate electrode. The second portion is distant from the gate electrode. An N-type doped silicon-containing structure is disposed over the diffusion barrier structure. The first portion of the diffusion barrier structure is configured to partially prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate. The second portion of the diffusion barrier structure is configured to substantially completely prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate.

    摘要翻译： 集成电路包括设置在基板上的栅电极。 源极/漏极（S / D）区域邻近栅电极设置。 S / D区域包括设置在基板的凹部中的扩散阻挡结构。 扩散阻挡结构包括第一部分和第二部分。 第一部分与栅电极相邻。 第二部分远离栅电极。 在扩散阻挡结构上设置N型掺杂的含硅结构。 扩散阻挡结构的第一部分被配置为部分地防止N型掺杂的含硅结构的N型掺杂剂扩散到衬底中。 扩散阻挡结构的第二部分被配置为基本上完全防止N型掺杂含硅结构的N型掺杂剂扩散到衬底中。