公开(公告)号：US5097237A

公开(公告)日：1992-03-17

申请号：US566532

申请日：1990-08-10

申请人： Tomokazu Komazaki ,  Katsuhiko Gunji ,  Norio Onishi ,  Ichiro Iwase ,  Akira Mashimo

发明人： Tomokazu Komazaki ,  Katsuhiko Gunji ,  Norio Onishi ,  Ichiro Iwase ,  Akira Mashimo

IPC分类号： H01P1/203 ,  H01P7/08

CPC分类号： H01P1/20381 ,  H01P7/082

摘要： A microstrip line type resonator includes a rectangular parallelapiped dielectric plate, and a conductive microstrip line disposed on a top surface of the dielectric plate. The microstrip line has opposite ends respectively spaced from front and rear edges of the dielectric plate. The resonator further includes a first grounding layer disposed on an entirety of the bottom surface of the dielectric plate, and a second grounding layer disposed an entirety of the front, rear and side surfaces of the dielectric plate. The first grounding layer is electrically connected to the second grounding layer at the edges of the bottom surface of the dielectric plate. The microstrip line type resonator is a 1/2 wavelength resonator.

摘要翻译： 微带线型谐振器包括矩形平行电介质板和布置在电介质板的顶表面上的导电微带线。 微带线具有分别与电介质板的前边缘和后边缘间隔开的相对端。 谐振器还包括设置在电介质板的整个底表面上的第一接地层和设置在电介质板的整个前，后和侧表面的第二接地层。 第一接地层在电介质板的底表面的边缘处电连接到第二接地层。 微带线型谐振器是1/2波长谐振器。

公开(公告)号：US5124675A

公开(公告)日：1992-06-23

申请号：US584176

申请日：1990-09-18

申请人： Tomokazu Komazaki ,  Katsuhiko Gunji ,  Norio Onishi ,  Ichiro Iwase ,  Akira Mashimo

发明人： Tomokazu Komazaki ,  Katsuhiko Gunji ,  Norio Onishi ,  Ichiro Iwase ,  Akira Mashimo

IPC分类号： H01P1/205

CPC分类号： H01P1/2056

摘要： An LC-type dielectric filter which includes strip lines on a dielectric plate forming distributed constant type resonators. The strip lines and other elements of the filter, such as coupling capacitances are plated onto the dielectric plate as printed circuits to realize a small, high-Q dielectric filter which is suitable for mass-production.

摘要翻译： 一种LC型介质滤波器，其在形成分布常数型谐振器的电介质板上包括带状线。 将滤波器的带状线和其它元件（例如耦合电容）作为印刷电路电镀在电介质板上，以实现适合于批量生产的小型高Q介质滤波器。

公开(公告)号：US07078984B2

公开(公告)日：2006-07-18

申请号：US10486719

申请日：2003-02-26

申请人： Eiju Komuro ,  Katsuhiko Gunji

发明人： Eiju Komuro ,  Katsuhiko Gunji

IPC分类号： H03H9/70 ,  H03H9/54

CPC分类号： H03H9/706 ,  H03H3/02 ,  H03H9/0571 ,  H03H9/132 ,  H03H9/175 ,  H03H9/564 ,  H03H9/568 ,  H04B1/52

摘要： A duplexer (1) comprises a chip (10) including a transmission filter (97) for passing a transmission signal therethrough and interrupting a reception signal and a reception filter (98) for passing a reception signal therethrough and interrupting a transmission signal. Each of the transmission filter (97) and the reception filter (98) includes thin-film piezoelectric resonators (16 and 17) each of which has a piezoelectric thin film that exhibits a piezoelectric property and two excitation electrodes that are disposed on both surfaces of the piezoelectric thin film and apply an excitation voltage to the piezoelectric thin film. All of the thin-film piezoelectric resonators (16 and 17) that the transmission filter (97) and the reception filter (98) include are disposed on a single base.

摘要翻译： 双工器（1）包括芯片（10），其包括用于通过传输信号并中断接收信号的传输滤波器（97）和用于通过接收信号并中断传输信号的接收滤波器（98）。 发送滤波器（97）和接收滤波器（98）中的每一个均包括薄膜压电谐振器（16和17），每个薄膜压电谐振器具有压电性能的压电薄膜和设置在两个表面上的压电特性的两个激励电极 压电薄膜，并向压电薄膜施加激发电压。 发送滤波器（97）和接收滤波器（98）包括的所有薄膜压电谐振器（16和17）都设置在单个基座上。

公开(公告)号：US20060134834A1

公开(公告)日：2006-06-22

申请号：US11333316

申请日：2006-01-18

申请人： Masahiro Nakano ,  Katsuhiko Gunji ,  Yasunobu Oikawa ,  Katsuo Sato

发明人： Masahiro Nakano ,  Katsuhiko Gunji ,  Yasunobu Oikawa ,  Katsuo Sato

IPC分类号： H01L21/48

CPC分类号： H03H9/1071 ,  H01L2224/16225 ,  H01L2224/45144 ,  H03H9/0585 ,  H03H9/059 ,  H03H9/08 ,  H01L2924/00

摘要： A basic portion layer 21 of a substrate electrode 12a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in the sintered substrate member is polished. On the polished basic portion layer 21, the plating layers 22, 23. are formed, so that surface roughness of the substrate electrode 12a may be, for example, not larger than 0.1 μmRMS Accordingly, junction strength of an integrated circuit element mounted on a packaging substrate by a flip-chip method can be improved.

摘要翻译： 衬底电极12a的基本部分层21，其在陶瓷的衬底构件上电连接到突出电极13。 对其上形成有碱性部分层21的基材进行烧结。 研磨烧结基板部件中的基体部分层21的表面。 在抛光的基底层21上，形成镀层22,23，使得基板电极12a的表面粗糙度例如可以不大于0.1μm。因此，集成电路元件的结合强度 可以提高通过倒装芯片方法的封装衬底。

公开(公告)号：US06977563B2

公开(公告)日：2005-12-20

申请号：US10670234

申请日：2003-09-26

申请人： Eiju Komuro ,  Masaaki Imura ,  Katsuhiko Gunji ,  Taku Takeishi ,  Roger William Whatmore ,  Joseph Edward Albert Southin

发明人： Eiju Komuro ,  Masaaki Imura ,  Katsuhiko Gunji ,  Taku Takeishi ,  Roger William Whatmore ,  Joseph Edward Albert Southin

IPC分类号： H03H3/02 ,  H03H3/04 ,  H03H9/02 ,  H03H9/17 ,  H03H9/56 ,  H03H9/58 ,  H03H9/70 ,  H03H9/00

CPC分类号： H03H9/564 ,  H03H3/04 ,  H03H9/02094 ,  H03H9/02149 ,  H03H9/173 ,  H03H9/174 ,  H03H2003/0428

摘要： A thin-film piezoelectric resonator including a piezoelectric thin film having piezoelectric characteristic, and an upper electrode and a lower electrode arranged on opposite surfaces of the piezoelectric thin film for applying an excitation voltage to the piezoelectric thin film, wherein: each of the upper electrode and the lower electrode includes a resonant portion, and a lead-out portion; and the electrode thickness of at least one part of the lead-out portion in at least one of the upper electrode and the lower electrode is larger than the electrode thickness of the resonant portion formed to be continued from the lead-out portion.

摘要翻译： 包括具有压电特性的压电薄膜的薄膜压电谐振器和布置在压电薄膜的相对表面上的上电极和下电极，用于向压电薄膜施加激励电压，其中：每个上电极 并且所述下电极包括谐振部分和引出部分; 并且上电极和下电极中的至少一个中的引出部分的至少一部分的电极厚度大于形成为从引出部分继续的谐振部分的电极厚度。

公开(公告)号：US07132310B2

公开(公告)日：2006-11-07

申请号：US11333316

申请日：2006-01-18

申请人： Masahiro Nakano ,  Katsuhiko Gunji ,  Yasunobu Oikawa ,  Katsuo Sato

发明人： Masahiro Nakano ,  Katsuhiko Gunji ,  Yasunobu Oikawa ,  Katsuo Sato

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H03H9/1071 ,  H01L2224/16225 ,  H01L2224/45144 ,  H03H9/0585 ,  H03H9/059 ,  H03H9/08 ,  H01L2924/00

摘要： A basic portion layer 21 of a substrate electrode 12a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in the sintered substrate member is polished. On the polished basic portion layer 21, the plating layers 22, 23are formed, so that surface roughness of the substrate electrode 12a may be, for example, not larger than 0.1 μmRMS. Accordingly, junction strength of an integrated circuit element mounted on a packaging substrate by a flip-chip method can be improved.

摘要翻译： 衬底电极12a的基本部分层21，其在陶瓷的衬底构件上电连接到突出电极13。 对其上形成有碱性部分层21的基材进行烧结。 研磨烧结基板部件中的基体部分层21的表面。 在抛光的基底层21上形成镀层22,23，使得基板电极12a的表面粗糙度例如可以不大于0.1μmumRMS。 因此，可以提高通过倒装芯片方法安装在封装基板上的集成电路元件的结合强度。

公开(公告)号：US07015556B2

公开(公告)日：2006-03-21

申请号：US10813393

申请日：2004-03-31

申请人： Masahiro Nakano ,  Katsuhiko Gunji ,  Yasunobu Oikawa ,  Katsuo Sato

发明人： Masahiro Nakano ,  Katsuhiko Gunji ,  Yasunobu Oikawa ,  Katsuo Sato

IPC分类号： H01L29/84 ,  H01L22/48

CPC分类号： H03H9/1071 ,  H01L2224/16225 ,  H01L2224/45144 ,  H03H9/0585 ,  H03H9/059 ,  H03H9/08 ,  H01L2924/00

摘要： A basic portion layer 21 of a substrate electrode 12a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in the sintered substrate member is polished. On the polished basic portion layer 21, the plating layers 22, 23 are formed, so that surface roughness of the substrate electrode 12a may be, for example, not larger than 0.1 μmRMS. Accordingly, junction strength of an integrated circuit element mounted on a packaging substrate by a flip-chip method can be improved.

摘要翻译： 衬底电极12a的基本部分层21，其在陶瓷的衬底构件上电连接到突出电极13。 对其上形成有碱性部分层21的基材进行烧结。 研磨烧结基板部件中的基体部分层21的表面。 在抛光的基底层21上形成镀层22,23，使得基板电极12a的表面粗糙度例如可以不大于0.1μmumRMS。 因此，可以提高通过倒装芯片方法安装在封装基板上的集成电路元件的结合强度。

公开(公告)号：US06778038B2

公开(公告)日：2004-08-17

申请号：US10260265

申请日：2002-10-01

申请人： Taku Takeishi ,  Katsuhiko Gunji ,  Eiju Komuro

发明人： Taku Takeishi ,  Katsuhiko Gunji ,  Eiju Komuro

IPC分类号： H03H970

CPC分类号： H03H9/02047 ,  H03H9/0523 ,  H03H9/605 ,  Y10T29/42

摘要： A piezoelectric resonant filter comprises a chip having a plurality of thin-film piezoelectric resonators, and a mounting substrate on which the chip is mounted. The chip is mounted on the mounting substrate by flip chip bonding. A plurality of bumps provided on the chip are bonded to a plurality of conductors on the mounting substrate by interdiffusion between atoms, in a solid phase, of the respective metals of which the bumps and the conductors are made, without involving melting of the respective metals of which the bumps and the conductors are made. The chip has a series resonator and a parallel resonator each formed of a thin-film piezoelectric resonator. These resonators constitute a ladder filter circuit.

摘要翻译： 压电谐振滤波器包括具有多个薄膜压电谐振器的芯片和安装芯片的安装基板。 芯片通过倒装芯片接合安装在安装基板上。 设置在芯片上的多个凸块通过在形成凸块和导体的相应金属的固相中的原子之间的相互扩散而不涉及相应金属的熔化而在安装基板上的多个导体上结合 其中制作了凸块和导体。 该芯片具有由薄膜压电谐振器形成的串联谐振器和并联谐振器。 这些谐振器构成梯形滤波器电路。