Mask pattern preparation method, semiconductor device manufacturing method and recording medium
    12.
    发明授权
    Mask pattern preparation method, semiconductor device manufacturing method and recording medium 失效
    掩模图案制备方法,半导体器件制造方法和记录介质

    公开(公告)号:US07793252B2

    公开(公告)日:2010-09-07

    申请号:US12222479

    申请日:2008-08-11

    IPC分类号: G06F17/50 G03F9/00

    CPC分类号: G03F7/70433 G03F7/705

    摘要: A lithography simulation method includes: taking in design data of a pattern to be formed on a substrate and mask data to prepare a mask pattern used in forming a latent image of the pattern on the substrate by transmission of an energy ray; obtaining the latent image of the pattern by calculation of an intensity of the energy ray; locally changing, at least in a portion corresponding to a pattern to be interested, a relative position in a direction of the intensity of the energy ray between a latent image curve and a reference intensity line in accordance with a distance between the pattern to be interested and a pattern of a neighboring region, the latent image curve being an intensity distribution curve of the energy ray constituting the latent image, the reference intensity line being defined to specify a position of an edge of the pattern to be interested; and calculating a distance between intersections of a portion of the latent image curve corresponding to the pattern to be interested and the reference intensity line in the changed relative position to define an interested line width of the pattern to be interested.

    摘要翻译: 光刻模拟方法包括:获取要在基板上形成的图案的设计数据,并且掩模数据,以通过透射能量线来制备用于在基板上形成图案的潜像所使用的掩模图案; 通过计算能量射线的强度来获得图案的潜像; 至少在与感兴趣的图案对应的部分中,根据感兴趣的图案之间的距离,在潜像图像曲线和参考强度线之间的能量射线的强度的方向上的相对位置 以及相邻区域的图案,所述潜像曲线是构成所述潜像的能量射线的强度分布曲线,所述基准强度线被定义为指定所述图案的边缘的位置; 以及计算与感兴趣的图案对应的潜在图像曲线的一部分的交点与变化的相对位置中的基准强度线之间的距离,以定义感兴趣的图案的感兴趣的线宽。

    Design layout preparing method
    13.
    发明授权
    Design layout preparing method 有权
    设计布局准备方法

    公开(公告)号:US07194704B2

    公开(公告)日:2007-03-20

    申请号:US11012491

    申请日:2004-12-16

    IPC分类号: G06F17/50 G06F9/45 G06F9/455

    CPC分类号: G06F17/5081 H01L21/0271

    摘要: There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.

    摘要翻译: 公开了一种通过优化设计规则,过程接近校正参数和过程参数中的至少一个来生成设计布局的方法,包括基于设计布局和过程参数来计算处理的图案形状,提取具有评估的危险点 相对于不满足预定公差的加工图案形状的值,基于包含在危险点中的图案生成设计布局的修理指南,并且修复与危险点对应的设计布局的那部分 在维修准则上。

    Design pattern correcting method, design pattern forming method, process proximity effect correcting method, semiconductor device and design pattern correcting program
    14.
    发明申请
    Design pattern correcting method, design pattern forming method, process proximity effect correcting method, semiconductor device and design pattern correcting program 审中-公开
    设计模式校正方法,设计模式形成方法,过程接近效应校正方法,半导体器件和设计模式校正程序

    公开(公告)号:US20050251781A1

    公开(公告)日:2005-11-10

    申请号:US11115322

    申请日:2005-04-27

    CPC分类号: G03F1/36

    摘要: A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

    摘要翻译: 公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法,其包括提取从设计图案的顶点延伸的两个边缘中的至少一个,测量提取的边缘的长度, 确定测量的边缘的长度是否短于预定值,如果确定提取的边缘的长度短于预定值,则提取连接到所提取的边缘的两个顶点,并且重新设计匹配的设计模式 两个提取的顶点的位置彼此相对。

    Pattern verification method, pattern verification system, mask manufacturing method and semiconductor device manufacturing method
    15.
    发明申请
    Pattern verification method, pattern verification system, mask manufacturing method and semiconductor device manufacturing method 失效
    模式验证方法,模式验证系统,掩模制造方法和半导体器件制造方法

    公开(公告)号:US20050153217A1

    公开(公告)日:2005-07-14

    申请号:US11012494

    申请日:2004-12-16

    CPC分类号: G03F7/70441 G03F1/36

    摘要: A pattern verification method comprising preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges, the positional displacement being displacement between first point and the evaluation point, computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.

    摘要翻译: 一种图案验证方法,包括在衬底上制备期望图案和形成期望图案的掩模图案,在期望图案的边缘上限定至少一个评估点,限定至少一个工艺参数以计算所转印/形成的图案,定义 对于每个过程参数的参考值和可变范围,计算与评估点相对应的每个第一点的位置位移,使用校正掩模图案计算的第一点和通过改变其中的处理参数而获得的参数值的多个组合 可变范围或在各个可变范围内,位置偏移是第一点和评估点之间的位移,计算每个评估点的位置偏移的统计,以及根据统计信息输出修改掩模图案的信息。

    METHOD OF OPTIMIZING SEMICONDUCTOR DEVICE MANUFACTURING PROCESS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND NON-TRANSITORY COMPUTER READABLE MEDIUM
    16.
    发明申请
    METHOD OF OPTIMIZING SEMICONDUCTOR DEVICE MANUFACTURING PROCESS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND NON-TRANSITORY COMPUTER READABLE MEDIUM 审中-公开
    优化半导体器件制造工艺的方法,制造半导体器件的方法和非电子计算机可读介质

    公开(公告)号:US20120198396A1

    公开(公告)日:2012-08-02

    申请号:US13237854

    申请日:2011-09-20

    IPC分类号: G06F17/50

    摘要: A method of optimizing a semiconductor device manufacturing process according to an embodiment is a method of optimizing a semiconductor device manufacturing process in which a pattern based on circuit design is formed. The method of optimizing a semiconductor device manufacturing process according to the embodiment includes: at the time of calculation of a statistic amount based on a distribution of differences at a plurality of sites between a pattern formed by a first exposing apparatus in a first condition and a pattern formed by a second exposing apparatus in a second condition, calculating the statistic amount after applying weighting to the differences based on information on an electrical characteristic; and repeating the calculating with the second condition being changed, and selecting an condition in which the total sum becomes a minimum or equal to or less than a standard value as an optimized condition of the second exposing apparatus.

    摘要翻译: 根据实施例的优化半导体器件制造工艺的方法是优化其中形成基于电路设计的图案的半导体器件制造工艺的方法。 根据实施例的半导体器件制造方法的优化方法包括:在基于在第一状态下由第一曝光装置形成的图案与第一状态之间的多个位置处的差异的分布的统计量的计算时, 在第二状态下由第二曝光装置形成的图案,基于关于电特性的信息对所述差进行加权计算后的统计量; 并重复进行第二条件的计算,并且选择总和变为最小或等于或小于标准值的条件作为第二曝光装置的优化条件。

    Method and system for correcting a mask pattern design
    17.
    发明授权
    Method and system for correcting a mask pattern design 失效
    用于校正掩模图案设计的方法和系统

    公开(公告)号:US08078996B2

    公开(公告)日:2011-12-13

    申请号:US12457751

    申请日:2009-06-19

    IPC分类号: G06F17/50

    CPC分类号: G03F7/70441 G03F1/36

    摘要: A pattern verification method includes preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, and computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges. The positional displacement is a displacement between first point and the evaluation point. The method further includes computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.

    摘要翻译: 模式验证方法包括在衬底上制备期望图案和形成期望图案的掩模图案,在期望图案的边缘上限定至少一个评估点,限定至少一个过程参数以计算所转移/形成的图案,定义 针对每个处理参数的参考值和可变范围,并且计算与评估点相对应的每个第一点的位置偏移,使用校正掩模图案计算的第一点和通过改变处理参数获得的参数值的多个组合 在可变范围内或在相应的可变范围内。 位置偏移是第一点与评价点之间的位移。 该方法还包括计算每个评估点的位置偏移的统计量,并根据统计信息输出修改掩模图案的信息。

    SUB-RESOLUTION ASSIST FEATURE ARRANGING METHOD AND COMPUTER PROGRAM PRODUCT AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    18.
    发明申请
    SUB-RESOLUTION ASSIST FEATURE ARRANGING METHOD AND COMPUTER PROGRAM PRODUCT AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
    分解辅助功能安装方法和计算机程序产品和半导体器件的制造方法

    公开(公告)号:US20110294239A1

    公开(公告)日:2011-12-01

    申请号:US13051961

    申请日:2011-03-18

    IPC分类号: H01L21/66 G06F17/50

    CPC分类号: G03F1/36

    摘要: According to a sub-resolution assist feature arranging method in embodiments, it is selected which of a rule base and a model base is set for which pattern region on pattern data corresponding to a main pattern as a type of the method of arranging the sub-resolution assist feature for improving resolution of the main pattern formed on a substrate. Then, the sub-resolution assist feature by the rule base is arranged in a pattern region set as the rule base and the sub-resolution assist feature by the model base is arranged in a pattern region set as the model base.

    摘要翻译: 根据实施例中的子分辨率辅助特征排列方法,选择规则库和模型库中的哪一个被设置为对应于主图案的图案数据上的哪个图案区域作为安排子图形的方法的类型, 分辨率辅助功能,用于提高在基板上形成的主图案的分辨率。 然后,将规则库的子分辨率辅助特征设置在设置为规则库的图案区域中,并且由模型库将子分辨率辅助特征排列在设置为模型库的图案区域中。

    Design Pattern correcting method, process proximity effect correcting method, and semiconductor device manufacturing method
    19.
    发明授权
    Design Pattern correcting method, process proximity effect correcting method, and semiconductor device manufacturing method 失效
    设计图案校正方法,过程接近效应校正方法和半导体器件制造方法

    公开(公告)号:US07949967B2

    公开(公告)日:2011-05-24

    申请号:US12269705

    申请日:2008-11-12

    IPC分类号: G06F17/50

    CPC分类号: G03F1/36

    摘要: A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

    摘要翻译: 公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法,其包括提取从设计图案的顶点延伸的两个边缘中的至少一个,测量提取的边缘的长度, 确定测量的边缘的长度是否短于预定值,如果确定提取的边缘的长度短于预定值,则提取连接到所提取的边缘的两个顶点,并且重新设计匹配的设计模式 两个提取的顶点的位置彼此。

    Lithography simulation method, mask pattern preparation method, semiconductor device manufacturing method and recording medium
    20.
    发明申请
    Lithography simulation method, mask pattern preparation method, semiconductor device manufacturing method and recording medium 失效
    光刻模拟法,掩模图案制备方法,半导体器件制造方法和记录介质

    公开(公告)号:US20090019418A1

    公开(公告)日:2009-01-15

    申请号:US12222479

    申请日:2008-08-11

    IPC分类号: G06F17/50 G06K9/00

    CPC分类号: G03F7/70433 G03F7/705

    摘要: A lithography simulation method includes: taking in design data of a pattern to be formed on a substrate and mask data to prepare a mask pattern used in forming a latent image of the pattern on the substrate by transmission of an energy ray; obtaining the latent image of the pattern by calculation of an intensity of the energy ray; locally changing, at least in a portion corresponding to a pattern to be interested, a relative position in a direction of the intensity of the energy ray between a latent image curve and a reference intensity line in accordance with a distance between the pattern to be interested and a pattern of a neighboring region, the latent image curve being an intensity distribution curve of the energy ray constituting the latent image, the reference intensity line being defined to specify a position of an edge of the pattern to be interested; and calculating a distance between intersections of a portion of the latent image curve corresponding to the pattern to be interested and the reference intensity line in the changed relative position to define an interested line width of the pattern to be interested.

    摘要翻译: 光刻模拟方法包括:获取要在基板上形成的图案的设计数据,并且掩模数据,以通过透射能量线来制备用于在基板上形成图案的潜像所使用的掩模图案; 通过计算能量射线的强度来获得图案的潜像; 至少在与感兴趣的图案对应的部分中,根据感兴趣的图案之间的距离,在潜像图像曲线和参考强度线之间的能量射线的强度的方向上的相对位置 以及相邻区域的图案,所述潜像曲线是构成所述潜像的能量射线的强度分布曲线,所述基准强度线被定义为指定所述图案的边缘的位置; 以及计算与感兴趣的图案对应的潜在图像曲线的一部分的交点与变化的相对位置中的基准强度线之间的距离,以定义感兴趣的图案的感兴趣的线宽。