-
公开(公告)号：US20100259968A1
公开(公告)日：2010-10-14
申请号：US12747413
申请日：2008-12-11
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2213/56 , G11C2213/79
摘要： A storage device that improves ability of adjusting a resistance value level in recording and enables stable verification control is provided. VWL supplied from a second power source to a control terminal of a transistor is increased (increase portion: ΔVWL) for every rerecording by verification control by a WL adjustment circuit. In the case where a variable resistive element is able to record multiple values, ΔVWL is a value variable for every resistance value level of multiple value information. That is, ΔVWL is a value variable according to magnitude relation of a variation range of recording resistance of the variable resistive element due to a current. In the region where the variation range of the recording resistance is large (source-gate voltage VGS of the transistor is small), ΔVWL is small, while in the region where the variation range of the recording resistance is small (VGS is large), ΔVWL is large.
摘要翻译： 提供一种存储装置，其提高了在记录中调整电阻值电平的能力并且实现了稳定的验证控制。 通过WL调整电路的验证控制，每次重新录制时，从第二电源向晶体管的控制端子提供的VWL增加（增加部分：＆Dgr; VWL）。 在可变电阻元件能够记录多个值的情况下，＆Dgr; VWL是多值信息的每个电阻值电平的值变量。 也就是说，＆Dgr; VWL是根据由于电流引起的可变电阻元件的记录电阻的变化范围的大小关系的值变量。 在记录电阻的变化范围大（晶体管的源极栅极电压VGS小）的区域中，＆Dgr; VWL小，而在记录电阻的变化范围小（VGS大的区域） ），＆Dgr; VWL很大。
-
公开(公告)号：US20100254178A1
公开(公告)日：2010-10-07
申请号：US12745952
申请日：2008-12-11
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C11/56 , G11C13/0011 , G11C13/0069 , G11C2013/0071 , G11C2013/0092 , G11C2213/11 , G11C2213/56 , G11C2213/79
摘要： A storage device capable of reducing a number of cycles necessary for a verify at a time of multi-value recording is provided. An initial value of a potential difference VCG between a gate and a source of a switching transistor at the time of the verify is set to a value varied in accordance with a resistance value level of multi-value information. In the case where a writing side performs a 3-value recording, when “01” is the information, an initial value VGS01 is set to be smaller than VGS=1.7 V corresponding to the target resistance value level “01”, and when “00” is the information, a value is set to be lower than VGS=2.2 V corresponding to the target resistance value level “00” and higher than the above-described VGS01. This can reduce the number of cycles necessary for the verify process.
摘要翻译： 提供能够减少多值记录时的验证所需的循环次数的存储装置。 在验证时，开关晶体管的栅极和源极之间的电位差VCG的初始值被设定为根据多值信息的电阻值电平而变化的值。 在写入方执行3值记录的情况下，当“01”是信息时，初始值VGS01被设定为小于对应于目标电阻值电平“01”的VGS = 1.7V，当“ 00“是相对于目标电阻值电平”00“，高于上述VGS01的VGS = 2.2V的值。 这可以减少验证过程所需的周期数。
-
公开(公告)号：US07583525B2
公开(公告)日：2009-09-01
申请号：US11738933
申请日：2007-04-23
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2013/0092 , G11C2213/11 , G11C2213/51
摘要： A method of driving a storage device including a variable resistance element in which resistance value is changed reversibly between a high resistance state and a low resistance state by applying voltages with different polarities between two electrodes is provided. The storage device includes a plurality of memory cells formed of the variable resistance elements. The method includes the step of applying voltages more than once in combination to the memory cell when the variable resistance element is changed from the low resistance state to the high resistance state.
摘要翻译： 提供了一种通过在两个电极之间施加不同极性的电压来驱动包括可变电阻元件的存储装置的方法，其中电阻值在高电阻状态和低电阻状态之间可逆地改变。 存储装置包括由可变电阻元件形成的多个存储单元。 该方法包括当可变电阻元件从低电阻状态改变为高电阻状态时，将多次电压组合施加到存储单元的步骤。
-
公开(公告)号：US08576608B2
公开(公告)日：2013-11-05
申请号：US13310839
申请日：2011-12-05
申请人： Tomohito Tsushima , Makoto Kitagawa , Tsunenori Shiimoto , Chieko Nakashima , Hiroshi Yoshihara , Kentaro Ogata
发明人： Tomohito Tsushima , Makoto Kitagawa , Tsunenori Shiimoto , Chieko Nakashima , Hiroshi Yoshihara , Kentaro Ogata
CPC分类号： G11C13/0069 , G11C11/5614 , G11C13/0011 , G11C13/004 , G11C2013/0042 , H01L27/101 , H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/146
摘要： A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.
摘要翻译： 存储装置包括：多个存储单元，包括第一电阻变化元件; 以及读出电路，其通过将从所述多个存储单元中选择的存储单元的电阻状态与参考存储单元的电阻状态进行比较来确定所述第一电阻变化元件的电阻值的大小，其中所述参考存储器 单元包括第二电阻变化元件，第二电阻变化元件相对于施加电压的电阻值小于第一电阻变化元件的高电阻状态的电阻值，第二电阻变化元件显示相同的电阻变化 特征为第一电阻变化元件。
-
公开(公告)号：US08570787B2
公开(公告)日：2013-10-29
申请号：US13397282
申请日：2012-02-15
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2213/79
摘要： A storage apparatus includes: a plurality of storage elements configured to have the resistance state thereof changed in accordance with an applied voltage; and a drive portion configured to perform a resistance change operation and a read operation, the resistance change operation involving writing or erasing information to or from the storage elements by changing the resistance state thereof, the read operation involving reading the information from the storage elements; wherein the drive portion includes an amplifier configured to output a read signal upon execution of the read operation, a constant current load, and a control portion configured to perform the resistance change operation and a direct verify operation on the storage elements, the direct verify operation involving carrying out, subsequent to the resistance change operation, the read operation for verifying whether the writing or erasing of the information to or from the storage elements has been normally accomplished.
摘要翻译： 存储装置包括：多个存储元件，其被配置为根据施加的电压使其电阻状态发生变化; 以及驱动部，被配置为执行电阻变化操作和读取操作，所述电阻改变操作涉及通过改变其电阻状态来从存储元件写入或擦除信息，所述读取操作涉及从存储元件读取信息; 其特征在于，所述驱动部具有：放大器，被配置为在执行所述读取操作时输出读取信号;恒定电流负载;以及被配置为对所述存储元件执行电阻变化操作和直接验证操作的控制部，所述直接验证操作 涉及在电阻变化操作之后进行用于验证是否正常地完成对存储元件的写入或擦除信息的读取操作。
-
公开(公告)号：US08416602B2
公开(公告)日：2013-04-09
申请号：US12929384
申请日：2011-01-20
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C7/1048 , G11C7/12 , G11C13/0004 , G11C13/0007 , G11C13/0061 , G11C2013/0054
摘要： A nonvolatile semiconductor memory device includes: a memory element in which a rate of charge discharge between two electrodes of the memory element differs according to a logical value of stored information; cell wiring connected to one electrode of the memory element; a sense amplifier having a sense node connected to the cell wiring, the sense amplifier reading the logical value of the information by comparing a potential of the sense node with a reference potential; and a readout control circuit capable of switching between a dynamic sense operation performing readout by precharging the cell wiring and discharging or charging the cell wiring via the memory element and a static sense operation performing readout in a state of a current load being connected to the sense node.
摘要翻译： 非易失性半导体存储器件包括：存储元件，其中存储元件的两个电极之间的电荷放电速率根据存储的信息的逻辑值而不同; 连接到存储元件的一个电极的单元布线; 感测放大器，其具有连接到单元布线的感测节点，读出放大器通过将感测节点的电位与参考电位进行比较来读取信息的逻辑值; 以及读出控制电路，其能够通过对单元布线进行预充电并且经由存储元件对单元布线进行放电或充电而进行读出的动态感测操作之间切换，以及在与该感测连接的当前负载的状态下执行读出的静态感测操作 节点。
-
公开(公告)号：US20120212994A1
公开(公告)日：2012-08-23
申请号：US13310839
申请日：2011-12-05
申请人： Tomohito Tsushima , Makoto Kitagawa , Tsunenori Shiimoto , Chieko Nakashima , Hiroshi Yoshihara , Kentaro Ogata
发明人： Tomohito Tsushima , Makoto Kitagawa , Tsunenori Shiimoto , Chieko Nakashima , Hiroshi Yoshihara , Kentaro Ogata
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/5614 , G11C13/0011 , G11C13/004 , G11C2013/0042 , H01L27/101 , H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/146
摘要： A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.
摘要翻译： 存储装置包括：多个存储单元，包括第一电阻变化元件; 以及读出电路，其通过将从所述多个存储单元中选择的存储单元的电阻状态与参考存储单元的电阻状态进行比较来确定所述第一电阻变化元件的电阻值的大小，其中所述参考存储器 单元包括第二电阻变化元件，第二电阻变化元件相对于施加电压的电阻值小于第一电阻变化元件的高电阻状态的电阻值，第二电阻变化元件显示相同的电阻变化 特征为第一电阻变化元件。
-
公开(公告)号：US20110199812A1
公开(公告)日：2011-08-18
申请号：US12929384
申请日：2011-01-20
CPC分类号： G11C13/004 , G11C7/1048 , G11C7/12 , G11C13/0004 , G11C13/0007 , G11C13/0061 , G11C2013/0054
摘要： A nonvolatile semiconductor memory device includes: a memory element in which a rate of charge discharge between two electrodes of the memory element differs according to a logical value of stored information; cell wiring connected to one electrode of the memory element; a sense amplifier having a sense node connected to the cell wiring, the sense amplifier reading the logical value of the information by comparing a potential of the sense node with a reference potential; and a readout control circuit capable of switching between a dynamic sense operation performing readout by precharging the cell wiring and discharging or charging the cell wiring via the memory element and a static sense operation performing readout in a state of a current load being connected to the sense node.
摘要翻译： 非易失性半导体存储器件包括：存储元件，其中存储元件的两个电极之间的电荷放电速率根据存储的信息的逻辑值而不同; 连接到存储元件的一个电极的单元布线; 感测放大器，其具有连接到单元布线的感测节点，读出放大器通过将感测节点的电位与参考电位进行比较来读取信息的逻辑值; 以及读出控制电路，其能够通过对单元布线进行预充电并且经由存储元件对单元布线进行放电或充电而进行读出的动态感测操作之间切换，以及在与该感测连接的当前负载的状态下执行读出的静态感测操作 节点。
-
公开(公告)号：US20110149635A1
公开(公告)日：2011-06-23
申请号：US12747832
申请日：2008-12-11
CPC分类号： G11C13/0007 , G11C13/0004 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/009 , G11C2213/56 , G11C2213/79 , G11C2213/82
摘要： A storage device capable of decreasing the number of voltages necessitating control and decreasing peripheral circuit size is provided. A first pulse voltage (VBLR) is supplied from a first power source through a bit line BLR to an electrode of a variable resistive element. A second pulse voltage (VWL) for selecting a cell is supplied from a second power source through a word line WL to a control terminal of a transistor. A third pulse voltage (VBLT) is supplied from a third power source though a bit line BLT to a second input/output terminal of the transistor. At the time of rewriting information, the voltage value (VBLT) of the third power source is adjusted by an adjustment circuit. Thereby, a cell voltage and a cell current are changed (decreased or increased).
摘要翻译： 提供能够减少需要控制和减小外围电路尺寸的电压数量的存储装置。 第一脉冲电压（VBLR）从第一电源通过位线BLR提供给可变电阻元件的电极。 用于选择单元的第二脉冲电压（VWL）从第二电源通过字线WL提供给晶体管的控制端。 第三脉冲电压（VBLT）通过位线BLT从第三电源提供给晶体管的第二输入/输出端。 在重写信息时，通过调整电路来调整第三电源的电压值（VBLT）。 由此，电池电压和电池电流发生变化（减少或增加）。
-
公开(公告)号：US20110026298A1
公开(公告)日：2011-02-03
申请号：US12671939
申请日：2008-08-12
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/0092 , G11C2213/56 , H01L27/101 , H01L45/085 , H01L45/1266 , H01L45/146
摘要： Provided is a method of driving a storage device capable of improving reliability of data write in the storage device including a variable resistance element. At the time of data write operation, a plurality of write pulses having shapes different from each other are applied between electrodes 21 and 24 in a variable resistance element 2. Diffusion loss of a conductive path caused by self-heat generation (generation of Joule heat) of the variable resistance element 2 may be prevented, and thus data hold operation after write is stabilized. Also, the variable resistance element 2 may be prevented from being destructed when the write operation is sufficiently performed, and thus the data write operation is stabilized.
摘要翻译： 提供一种驱动能够提高包括可变电阻元件的存储装置中的数据写入的可靠性的存储装置的方法。 在数据写入操作时，在可变电阻元件2中的电极21和24之间施加具有彼此不同形状的多个写入脉冲。由自发热引起的导电路径的扩散损耗（产生焦耳热 ）可以防止可变电阻元件2的数据保持操作。 此外，当充分执行写入操作时，可以防止可变电阻元件2被破坏，从而使数据写入操作稳定。
-
-
-
-
-
-
-
-
-
搜索结果
57 条记录 (耗时 0.035 秒)
