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26 条记录 (耗时 0.019 秒)

    Receiver circuit
    11.
    发明授权
    Receiver circuit 有权
    接收电路

    公开(公告)号：US07675314B2

    公开(公告)日：2010-03-09

    申请号：US12081154

    申请日：2008-04-11

    申请人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

    发明人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

    IPC分类号： H03K19/007

    CPC分类号： H04L25/493

    摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

    摘要翻译： 在通过电缆接收数据和时钟信号的接收机电路中，通过频率检测电路检测基于数据或时钟信号获得的信号的转变次数，并且当转换次数不大于预定的集合 输出用于复位包括在数据处理单元中的串行 - 并行转换器电路的操作的信号，以便控制接收数据的输出。 因此，在不提供上拉电阻器和下拉电阻器的情况下，可以以低功耗检测电缆的断开，并且可以提高抗噪声性能。

    CLOCK GENERATION CIRCUIT
    12.
    发明申请
    CLOCK GENERATION CIRCUIT 有权
    时钟发生电路

    公开(公告)号：US20090284297A1

    公开(公告)日：2009-11-19

    申请号：US12095094

    申请日：2006-11-30

    申请人： Tsuyoshi Ebuchi

    发明人： Tsuyoshi Ebuchi

    IPC分类号： G06F1/04

    CPC分类号： H03L7/093 ,  G06F1/08

    摘要： A multiphase clock generation circuit (111) for generating a multiphase cock signal, a phase subdivision unit (113) for shifting a phase of the multiphase clock signal output from the multiphase clock generation circuit (111), and a clock selection unit (114) for selecting one of clock signals output from the phase subdivision unit (113) are provided. A PLL circuit (120) for receiving an output from a frequency division circuit (115) is further provided. The phase shift carried out by the phase subdivision unit (113) and the selection of the clock signal carried out by the clock selection unit (114) are controlled by a frequency control unit (112) to switch SSC ON/OFF and to change the bandwidth of the PLL circuit (120).

    摘要翻译： 一种用于产生多相旋转信号的多相时钟产生电路（111），用于移位从多相时钟产生电路（111）输出的多相时钟信号的相位的相位细分单元（113），以及时钟选择单元（114） 用于选择从相位细分单元（113）输出的时钟信号之一。 还提供了用于接收来自分频电路（115）的输出的PLL电路（120）。 由相位细分单元（113）执行的相移和由时钟选择单元（114）执行的时钟信号的选择由频率控制单元（112）控制，以切换SSC的ON / OFF并改变 PLL电路（120）的带宽。

    Receiver circuit
    13.
    发明授权
    Receiver circuit 有权

    公开(公告)号：US07397268B2

    公开(公告)日：2008-07-08

    申请号：US11653340

    申请日：2007-01-16

    申请人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

    发明人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

    IPC分类号： H03K19/007

    CPC分类号： H04L25/493

    摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

    Receiver circuit
    14.
    发明申请
    Receiver circuit 有权

    公开(公告)号：US20070115025A1

    公开(公告)日：2007-05-24

    申请号：US11653340

    申请日：2007-01-16

    申请人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

    发明人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

    IPC分类号： H03K19/007

    CPC分类号： H04L25/493

    摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

    PLL circuit
    16.
    发明授权
    PLL circuit 有权
    PLL电路

    公开(公告)号：US07898305B2

    公开(公告)日：2011-03-01

    申请号：US12651061

    申请日：2009-12-31

    申请人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

    发明人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

    IPC分类号： H03L7/00

    CPC分类号： H03L7/10 ,  H03L7/085 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/1976

    摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

    摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号 （26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

    PLL circuit
    17.
    发明授权
    PLL circuit 有权
    PLL电路

    公开(公告)号：US07746132B2

    公开(公告)日：2010-06-29

    申请号：US12066000

    申请日：2006-07-27

    申请人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

    发明人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

    IPC分类号： H03L7/06

    CPC分类号： H03L7/10 ,  H03L7/085 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/1976

    摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

    摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号 （26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

    Frequency modulation circuit
    18.
    发明申请
    Frequency modulation circuit 有权
    频率调制电路

    公开(公告)号：US20050135505A1

    公开(公告)日：2005-06-23

    申请号：US11000224

    申请日：2004-12-01

    申请人： Tsuyoshi Ebuchi ,  Takefumi Yoshikawa ,  Yukio Arima

    发明人： Tsuyoshi Ebuchi ,  Takefumi Yoshikawa ,  Yukio Arima

    IPC分类号： H03C3/00 ,  H03K7/06 ,  H03L7/093 ,  H04B15/02 ,  H04B3/46

    CPC分类号： H04B15/02 ,  H03K7/06 ,  H04B2215/067

    摘要： The frequency modulation circuit includes: a phase shift section for receiving a multiphase clock signal composed of a plurality of clock signals having a predetermined phase difference therebetween and shifting the phase of the multiphase clock signal; a clock selection section for selecting a clock signal constituting the multiphase clock signal output from the phase shift section; and a modulation control section for controlling the phase shift section and the clock selection section so that a clock signal having a frequency different from the frequency of the multiphase clock signal input into the phase shift section is output from the clock selection section.

    摘要翻译： 频率调制电路包括：相移部，用于接收由多个时钟信号组成的多相时钟信号，所述多个时钟信号具有预定的相位差，并移位多相时钟信号的相位; 时钟选择部分，用于选择构成从相移部分输出的多相时钟信号的时钟信号; 以及调制控制部分，用于控制相移部分和时钟选择部分，使得从时钟选择部分输出具有与输入到相移部分的多相时钟信号的频率不同的频率的时钟信号。

    PLL CIRCUIT
    19.
    发明申请
    PLL CIRCUIT 审中-公开
    PLL电路

    公开(公告)号：US20110115531A1

    公开(公告)日：2011-05-19

    申请号：US13014362

    申请日：2011-01-26

    申请人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

    发明人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

    IPC分类号： H03L7/095 ,  H03B19/00 ,  H03L7/10

    CPC分类号： H03L7/10 ,  H03L7/085 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/1976

    摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

    摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号 （26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

    Frequency modulation circuit
    20.
    发明授权
    Frequency modulation circuit 有权
    频率调制电路

    公开(公告)号：US07233215B2

    公开(公告)日：2007-06-19

    申请号：US11000224

    申请日：2004-12-01

    申请人： Tsuyoshi Ebuchi ,  Takefumi Yoshikawa ,  Yukio Arima

    发明人： Tsuyoshi Ebuchi ,  Takefumi Yoshikawa ,  Yukio Arima

    IPC分类号： H03C3/00

    CPC分类号： H04B15/02 ,  H03K7/06 ,  H04B2215/067

    摘要： The frequency modulation circuit includes: a phase shift section for receiving a multiphase clock signal composed of a plurality of clock signals having a predetermined phase difference therebetween and shifting the phase of the multiphase clock signal; a clock selection section for selecting a clock signal constituting the multiphase clock signal output from the phase shift section; and a modulation control section for controlling the phase shift section and the clock selection section so that a clock signal having a frequency different from the frequency of the multiphase clock signal input into the phase shift section is output from the clock selection section.

    摘要翻译： 频率调制电路包括：相移部，用于接收由多个时钟信号组成的多相时钟信号，所述多个时钟信号具有预定的相位差，并移位多相时钟信号的相位; 时钟选择部分，用于选择构成从相移部分输出的多相时钟信号的时钟信号; 以及调制控制部分，用于控制相移部分和时钟选择部分，使得从时钟选择部分输出具有与输入到相移部分的多相时钟信号的频率不同的频率的时钟信号。