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26 条记录 (耗时 0.017 秒)

    Hybrid data transmission circuit
    5.
    发明授权
    Hybrid data transmission circuit 有权
    混合数据传输电路

    公开(公告)号：US08265195B2

    公开(公告)日：2012-09-11

    申请号：US13242962

    申请日：2011-09-23

    申请人： Tsuyoshi Ebuchi ,  Yoshihide Komatsu

    发明人： Tsuyoshi Ebuchi ,  Yoshihide Komatsu

    IPC分类号： H04L27/00 ,  H03D3/24

    CPC分类号： H04L25/028 ,  H03K3/0322 ,  H03K5/15093 ,  H03L7/081 ,  H03L7/0995 ,  H03L2207/06 ,  H03M9/00 ,  H04L7/0337 ,  H04L25/0272

    摘要： A data transmitter having a parallel-to-serial conversion function is supplied with a clock by a PLL circuit unit. In the PLL circuit unit, a first multiphase clock supplied to a first parallel-to-serial conversion circuit is generated and output by a multiphase VCO circuit, while a second multiphase clock supplied to a second parallel-to-serial conversion circuit is generated and output by a multiphase clock generator. The multiphase clock generator generates the second multiphase clock based on the clock output from the multiphase VCO circuit.

    摘要翻译： 具有并行到串行转换功能的数据发射机由PLL电路单元提供时钟。 在PLL电路单元中，提供给第一并行转换电路的第一多相时钟由多相VCO电路产生并输出，同时产生提供给第二并行 - 串行转换电路的第二多相时钟， 由多相时钟发生器输出。 多相时钟发生器基于来自多相VCO电路的时钟输出产生第二多相时钟。

    Receiver circuit
    6.
    发明申请
    Receiver circuit 有权
    接收电路

    公开(公告)号：US20080315911A1

    公开(公告)日：2008-12-25

    申请号：US12081154

    申请日：2008-04-11

    申请人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

    发明人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

    IPC分类号： H03K19/007

    CPC分类号： H04L25/493

    摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

    摘要翻译： 在通过电缆接收数据和时钟信号的接收机电路中，通过频率检测电路检测基于数据或时钟信号获得的信号的转变次数，并且当转换次数不大于预定的集合 输出用于复位包括在数据处理单元中的串行 - 并行转换器电路的操作的信号，以便控制接收数据的输出。 因此，在不提供上拉电阻器和下拉电阻器的情况下，可以以低功耗检测电缆的断开，并且可以提高抗噪声性能。

    Driver circuit and data communication device
    7.
    发明授权
    Driver circuit and data communication device 有权

    公开(公告)号：US07016423B2

    公开(公告)日：2006-03-21

    申请号：US10058904

    申请日：2002-01-30

    申请人： Tsuyoshi Ebuchi ,  Takefumi Yoshikawa

    发明人： Tsuyoshi Ebuchi ,  Takefumi Yoshikawa

    IPC分类号： H04L25/00 ,  G05F1/10

    CPC分类号： H04L25/029 ,  H04L25/0276

    摘要： The driver circuit of the present invention includes: a drive section for generating a differential signal according to an input signal and outputting the signal to an electric cable or an optical transceiver; and a control section receiving a selection signal based on which the drive section selects to drive the electric cable or the optical transceiver, an identification signal, and a data signal, for generating a signal based on the received signals and outputting the generated signal to the drive section. During a period indicated by the identification signal, the control section controls the drive section to put the output of the drive section in a high impedance state when the selection signal indicates selection of the electric cable, or output a predetermined differential signal, not putting the output in a high impedance state, when the selection signal indicates selection of the optical transceiver.

    Phase comparator and clock recovery circuit
    8.
    发明授权
    Phase comparator and clock recovery circuit 有权
    相位比较器和时钟恢复电路

    公开(公告)号：US06853223B2

    公开(公告)日：2005-02-08

    申请号：US10345994

    申请日：2003-01-17

    申请人： Tsuyoshi Ebuchi ,  Takefumi Yoshikawa ,  Toru Iwata

    发明人： Tsuyoshi Ebuchi ,  Takefumi Yoshikawa ,  Toru Iwata

    IPC分类号： H03K5/26 ,  H03D13/00 ,  H03L7/08 ,  H03L7/087 ,  H03L7/089 ,  H04L7/033 ,  H03L7/06

    CPC分类号： H03D13/004 ,  H04L7/033

    摘要： The present invention aims at providing a phase comparator and a clock recovery circuit suitable for applications that support data signals with high-speed bit rates in the order of one gigabit per second. Phase comparators receive frequency divided signals NHOLDH and NHOLDL generated from a data signal RD/NRD, respectively, and intermittently perform a phase comparison between a signal dDAT and a signal CLK. This increases the timing margin for the phase comparison and makes it possible to perform a phase comparison for high-speed bit rate signals. The provision of phase comparators that serve as clock recovery circuits makes it possible to handle data signals with high-speed bit rates in the order of one gigabit per second.

    摘要翻译： 本发明的目的在于提供一种相位比较器和时钟恢复电路，适用于支持高速比特速率为每秒千兆位的数据信号的应用。 相位比较器分别接收从数据信号RD / NRD产生的分频信号NHOLDH和NHOLDL，并间歇地执行信号dDAT和信号CLK之间的相位比较。 这增加了相位比较的定时裕度，并且可以对高速比特率信号执行相位比较。 提供用作时钟恢复电路的相位比较器使得可以以高达1吉比特每秒的高速比特率来处理数据信号。

    Receiver circuit
    9.
    发明授权
    Receiver circuit 有权
    接收电路

    公开(公告)号：US07675314B2

    公开(公告)日：2010-03-09

    申请号：US12081154

    申请日：2008-04-11

    申请人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

    发明人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

    IPC分类号： H03K19/007

    CPC分类号： H04L25/493

    摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

    摘要翻译： 在通过电缆接收数据和时钟信号的接收机电路中，通过频率检测电路检测基于数据或时钟信号获得的信号的转变次数，并且当转换次数不大于预定的集合 输出用于复位包括在数据处理单元中的串行 - 并行转换器电路的操作的信号，以便控制接收数据的输出。 因此，在不提供上拉电阻器和下拉电阻器的情况下，可以以低功耗检测电缆的断开，并且可以提高抗噪声性能。

    CLOCK GENERATION CIRCUIT
    10.
    发明申请
    CLOCK GENERATION CIRCUIT 有权
    时钟发生电路

    公开(公告)号：US20090284297A1

    公开(公告)日：2009-11-19

    申请号：US12095094

    申请日：2006-11-30

    申请人： Tsuyoshi Ebuchi

    发明人： Tsuyoshi Ebuchi

    IPC分类号： G06F1/04

    CPC分类号： H03L7/093 ,  G06F1/08

    摘要： A multiphase clock generation circuit (111) for generating a multiphase cock signal, a phase subdivision unit (113) for shifting a phase of the multiphase clock signal output from the multiphase clock generation circuit (111), and a clock selection unit (114) for selecting one of clock signals output from the phase subdivision unit (113) are provided. A PLL circuit (120) for receiving an output from a frequency division circuit (115) is further provided. The phase shift carried out by the phase subdivision unit (113) and the selection of the clock signal carried out by the clock selection unit (114) are controlled by a frequency control unit (112) to switch SSC ON/OFF and to change the bandwidth of the PLL circuit (120).

    摘要翻译： 一种用于产生多相旋转信号的多相时钟产生电路（111），用于移位从多相时钟产生电路（111）输出的多相时钟信号的相位的相位细分单元（113），以及时钟选择单元（114） 用于选择从相位细分单元（113）输出的时钟信号之一。 还提供了用于接收来自分频电路（115）的输出的PLL电路（120）。 由相位细分单元（113）执行的相移和由时钟选择单元（114）执行的时钟信号的选择由频率控制单元（112）控制，以切换SSC的ON / OFF并改变 PLL电路（120）的带宽。