公开(公告)号：US5963476A

公开(公告)日：1999-10-05

申请号：US975516

申请日：1997-11-12

申请人： Chun Hsiung Hung ,  Tzeng-Huei Shiau ,  Yao-Wu Cheng ,  I-Long Lee ,  Fuchia Shone ,  Ray-Lin Wan

发明人： Chun Hsiung Hung ,  Tzeng-Huei Shiau ,  Yao-Wu Cheng ,  I-Long Lee ,  Fuchia Shone ,  Ray-Lin Wan

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  H01L27/115 ,  G11C16/06

CPC分类号： G11C16/107 ,  G11C16/0416 ,  G11C16/16 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/115

摘要： A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows pre-programming by Fowler Nordheim (F-N) tunneling over blocks of cells at a time. The floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunneling of electrons out of the floating gate into the channel area of the substrate for erasing by applying a positive voltage to the second well, such as a voltage higher than the supply voltage, applying a positive voltage to the first well, which is substantially equal to the positive voltage of the second well, applying a negative voltage to the control gate of the cell, while the substrate is grounded. A block wide pre-program operation involves F-N tunneling of electrons into the floating gate from the channel area, using a negative voltage in the second well.

摘要翻译： 新的闪存单元结构和操作偏置是基于使用三阱闪存单元，其允许Fowler Nordheim（F-N）一次在单元格块上进行预编程。 浮栅存储单元由具有第一导电类型的半导体衬底制成，例如p型。 包括具有不同于第一导电类型的第二导电类型的衬底内的第一阱。 还包括第一阱中的第二阱具有第一导电类型。 在具有第二导电类型的第二阱中形成漏极和源极，并且彼此间隔开以限定漏极和源极之间的沟道区域。 通道区域中包括浮动栅极和控制栅极结构。 浮动栅极存储单元与电路耦合，该电路通过向第二阱施加正电压，例如高于电源电压的电压，施加电压，使电子从浮动栅极进入隧道区域进入衬底的通道区域以进行擦除 与第一阱的正电压相比，其基本上等于第二阱的正电压，而在衬底接地时，向电池的控制栅极施加负电压。 块宽的预编程操作涉及使用第二阱中的负电压将电子从沟道区域F-N隧穿到浮置栅极。

公开(公告)号：US6087190A

公开(公告)日：2000-07-11

申请号：US973582

申请日：1997-11-17

申请人： Ray-Lin Wan ,  Chun-Hsiung Hung ,  Tzeng-Huei Shiau

发明人： Ray-Lin Wan ,  Chun-Hsiung Hung ,  Tzeng-Huei Shiau

IPC分类号： G11C29/24 ,  G11C29/44 ,  H10L21/00 ,  G01R31/26 ,  H10L21/66

CPC分类号： G11C29/24 ,  G11C29/44

摘要： A method of manufacturing integrated circuits based on providing a test column of memory cells in the devices. Cells in the test column are selected by a portion of the addresses which identifies a row in the main array on the device. A test is executed to determine a characteristic of the device, and the results of that test are mapped to the portion of the address which identifies a row in the array. This produces a characteristic code address for the device which indicates the results of the test. Access to the test column on the device is enabled, and a bit is written in response to the characteristic code address in a memory cell on the test column. During manufacture the test column is read in order to classify the device according to the characteristic. This allows for storing in a table look-up format, significant amounts of data about the characteristics of the device without requiring large amounts of memory on the device, and substantially relieving the testing system of a requirement for memory resources.

摘要翻译： PCT No.PCT / US97 / 18204 Sec。 371日期：1997年11月17日 102（e）日期1997年11月17日PCT 1997年10月8日PCT公布。 公开号WO99 /​​ 18531 日期1999年04月15日基于在器件中提供存储器单元的测试列的制造集成电路的方法。 测试列中的单元格由标识设备主阵列中的行的地址的一部分来选择。 执行测试以确定设备的特性，并将该测试的结果映射到标识阵列中的一行的地址部分。 这产生了指示测试结果的设备的特征代码地址。 启用对设备的测试列的访问，并响应于测试列上的存储单元中的特征代码地址写入一个位。 在制造期间，读取测试柱以便根据特性对装置进行分类。 这允许以表查找格式存储关于设备的特性的大量数据，而不需要设备上的大量存储器，并且基本上减轻了测试系统对存储器资源的需求。

公开(公告)号：US5998826A

公开(公告)日：1999-12-07

申请号：US817656

申请日：1997-04-04

申请人： Chun-Hsiung Hung ,  Tzeng-Huei Shiau ,  Ray-Lin Wan ,  Fu-Chia Shone

发明人： Chun-Hsiung Hung ,  Tzeng-Huei Shiau ,  Ray-Lin Wan ,  Fu-Chia Shone

IPC分类号： G11C16/16 ,  H01L29/788 ,  H01L27/76

CPC分类号： G11C16/16

摘要： A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows Fowler Nordheim (F-N) tunneling with lower absolute value bias potentials. Thus, the floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunneling of electrons out of the floating gate into the channel area of the substrate for erasing by applying a positive voltage to the second well, such as a voltage higher than the supply voltage, applying a positive voltage to the first well, which is substantially equal to the positive voltage of the second well, applying a negative voltage to the control gate of the cell, while the substrate is grounded. A block wide pre-program operation involves F-N tunneling of electrons into the floating gate from the channel area, using a negative voltage in the second well. Also, circuits are coupled with the cell to induce hot electron injection current of electrons into the floating gate for programming or byte by byte preprogramming.

摘要翻译： PCT No.PCT / US96 / 14349 Sec。 371日期1997年04月4日 102（e）日期1997年4月4日PCT 1996年9月5日PCT公布。 公开号WO98 / 10471 日期1998年3月12日新的闪存单元结构和操作偏置基于使用三阱闪存单元，这允许具有较低绝对值偏置电位的Fowler Nordheim（F-N）隧穿。 因此，浮置栅极存储单元被制成具有第一导电类型的诸如p型的半导体衬底。 包括具有不同于第一导电类型的第二导电类型的衬底内的第一阱。 还包括第一阱中的第二阱具有第一导电类型。 在具有第二导电类型的第二阱中形成漏极和源极，并且彼此间隔开以限定漏极和源极之间的沟道区域。 通道区域中包括浮动栅极和控制栅极结构。 浮动栅极存储单元与电路耦合，该电路通过向第二阱施加正电压，例如高于电源电压的电压，施加电压，使电子从浮动栅极进入隧道区域进入衬底的通道区域以进行擦除 与第一阱的正电压相比，其基本上等于第二阱的正电压，而在衬底接地时，向电池的控制栅极施加负电压。 块宽预编程操作涉及使用第二阱中的负电压将电子从沟道区域F-N隧穿到浮置栅极。 此外，电路与电池耦合以将电子的热电子注入电流引入浮动栅极进行编程或逐字节预编程。

公开(公告)号：US5805501A

公开(公告)日：1998-09-08

申请号：US718341

申请日：1996-10-03

申请人： Tzeng-Huei Shiau ,  Ray-Lin Wan ,  Weitong Chuang ,  Yu-Sui Lee ,  Kong Mou Liou

发明人： Tzeng-Huei Shiau ,  Ray-Lin Wan ,  Weitong Chuang ,  Yu-Sui Lee ,  Kong Mou Liou

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/16 ,  G11C2216/20

摘要： A flash memory device includes a multiple checkpoint erase suspend algorithm. A user may issue an erase suspend command at anytime during an erase process. The erase procedure is suspended as fast as possible by allowing the erase procedure to be suspended at the first to occur of a plurality of checkpoints in the process. The block erase procedure includes a precondition phase (also called a pre-programming phase), in which a selected block is pre-programmed by applying a program potential, and then the pre-programming of the block is verified on a byte-by-byte basis. After the precondition phase, an erase phase is executed in which the selected block is erased by applying an erase potential to the block, and then verifying the erasing of the block. Erase suspend logic is coupled to the erase logic and executes an erase suspend procedure which interrupts the block erase procedure after receiving the erase suspend command during the first to occur of a set of checkpoints in the block erase procedure. The set of checkpoints comprises a first checkpoint enabling the interrupting during the precondition phase, a second checkpoint enabling the interrupting during the application of the erase potential, a third checkpoint enabling the interrupting during the verifying of the erasing step, a fourth checkpoint between the precondition phase and the erase phase, and a fifth checkpoint after the erase pulse and before verifying the erase of the block. After interrupting the block erase procedure, the erase suspend procedure includes returning to the block erase procedure to complete the block erase.

摘要翻译： PCT No.PCT / US96 / 07491 Sec。 371日期：1996年10月3日 102（e）日期1996年10月3日PCT 1996年5月22日PCT公布。 WO97 / 44792 PCT出版物 日期1997年11月27日闪存器件包括多重检查点擦除挂起算法。 用户可以在擦除过程中随时发出擦除挂起命令。 擦除过程通过允许在该过程中首先发生多个检查点的第一次暂停，尽可能快地暂停该擦除过程。 块擦除过程包括预处理阶段（也称为预编程阶段），其中通过应用程序电位对所选择的块进行预编程，然后对块的预编程在逐字节校验上进行验证， 字节基础。 在预处理阶段之后，执行擦除阶段，通过向块施加擦除电位，然后验证块的擦除，擦除所选择的块。 擦除暂停逻辑被耦合到擦除逻辑，并且执行擦除暂停过程，该擦除暂停过程在块擦除过程中的一组检查点的第一次发生之后接收到擦除暂停命令之后中断块擦除过程。 所述检查点集合包括能够在预处理阶段期间进行中断的第一检查点，在施加擦除电位期间能够中断的第二检查点，在擦除步骤的验证期间能够中断的第三检查点，前提条件之间的第四检查点 相位和擦除相位，以及擦除脉冲后的第五个检查点，并且在验证块的擦除之前。 在中断块擦除过程之后，擦除暂停过程包括返回到块擦除过程以完成块擦除。

公开(公告)号：US5745410A

公开(公告)日：1998-04-28

申请号：US619485

申请日：1996-03-21

申请人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  I-Long Lee ,  Chia-Shing Chen ,  Hun-Song Chen ,  Yuan-Chang Liu ,  Tzeng-Huei Shiau ,  Kuen-Long Chang ,  Ray-Lin Wan

发明人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  I-Long Lee ,  Chia-Shing Chen ,  Hun-Song Chen ,  Yuan-Chang Liu ,  Tzeng-Huei Shiau ,  Kuen-Long Chang ,  Ray-Lin Wan

IPC分类号： G11C11/40

CPC分类号： G11C11/40

摘要： A floating gate memory device which includes control circuits to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block. This invention includes repairing the cells by applying a repair pulse to the cell's bit line while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.

摘要翻译： PCT No.PCT / US95 / 15051 Sec。 371日期1996年3月21日 102（e）1996年3月21日PCT 1995年11月17日PCT PCT。 第WO97 / 19452号公报 日期1997年5月29日一种浮动栅极存储器件，其包括产生修复脉冲以修复过擦除的单元的控制电路，使得它们可以逐块修复。 本发明包括通过在维持字线电压高于地面的同时将修复脉冲施加到单元的位线来修复单元。 在不同的实施例中，字线电压保持在地面以上两个不同的电压电平。 在第一阶段，当施加修复脉冲时，字线电压保持在大约0.1伏和0.2伏之间大约100毫秒。 在第二阶段，当施加修复脉冲时，字线电压保持在大约0.4伏和0.5伏之间大约100毫秒。

公开(公告)号：US20130285737A1

公开(公告)日：2013-10-31

申请号：US13460112

申请日：2012-04-30

申请人： Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

发明人： Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

IPC分类号： G05F3/02

CPC分类号： H02M3/07

摘要： In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.

摘要翻译： 在一个方面，第一电荷泵具有串联布置的电荷泵级。 相邻级之间的阶段节点由第二电荷泵泵送。 在另一方面，电荷泵级的定时由命令时钟信号控制。 命令时钟信号和命令数据在与电荷泵的集成电路和外部电路之间传送。

公开(公告)号：US07078761B2

公开(公告)日：2006-07-18

申请号：US10794564

申请日：2004-03-05

申请人： Alex Wang ,  Shang-De Ted Chang ,  Han-Chih Lin ,  Tzeng-Huei Shiau ,  I-Sheng Liu ,  Hsien-Wen Liu

发明人： Alex Wang ,  Shang-De Ted Chang ,  Han-Chih Lin ,  Tzeng-Huei Shiau ,  I-Sheng Liu ,  Hsien-Wen Liu

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/42328 ,  H01L29/7883

摘要： A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.

摘要翻译： 用于多次编程应用的单多晶双晶体管PMOS存储器单元包括共享漏极/源极P +扩散区的PMOS浮栅晶体管，其中PMOS选择栅晶体管全部形成在第一n阱内。 用于浮栅晶体管的控制板形成在第二n阱中。 用于一次编程应用的单晶双转移器PMOS存储器单元包括具有在单个n阱中形成为p +扩散区的源的PMOS浮栅晶体管。 源极也适用于浮栅晶体管的控制板。

公开(公告)号：US09214859B2

公开(公告)日：2015-12-15

申请号：US13460112

申请日：2012-04-30

申请人： Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

发明人： Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

IPC分类号： H02M3/07

CPC分类号： H02M3/07

摘要： In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.

摘要翻译： 在一个方面，第一电荷泵具有串联布置的电荷泵级。 相邻级之间的阶段节点由第二电荷泵泵送。 在另一方面，电荷泵级的定时由命令时钟信号控制。 命令时钟信号和命令数据在与电荷泵的集成电路和外部电路之间传送。

公开(公告)号：US07339229B2

公开(公告)日：2008-03-04

申请号：US11454916

申请日：2006-06-16

申请人： Alex Wang ,  Shang-De Ted Chang ,  Han-Chih Lin ,  Tzeng-Huei Shiau ,  I-Sheng Liu ,  Hsien-Wen Liu

发明人： Alex Wang ,  Shang-De Ted Chang ,  Han-Chih Lin ,  Tzeng-Huei Shiau ,  I-Sheng Liu ,  Hsien-Wen Liu

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/42328 ,  H01L29/7883

摘要： A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.

摘要翻译： 用于多次编程应用的单多晶双晶体管PMOS存储器单元包括共享漏极/源极P +扩散区的PMOS浮栅晶体管，其中PMOS选择栅晶体管全部形成在第一n阱内。 用于浮栅晶体管的控制板形成在第二n阱中。 用于一次编程应用的单晶双转移器PMOS存储器单元包括具有在单个n阱中形成为p +扩散区的源的PMOS浮栅晶体管。 源极也适用于浮栅晶体管的控制板。

公开(公告)号：US20060244043A1

公开(公告)日：2006-11-02

申请号：US11454916

申请日：2006-06-16

申请人： Alex Wang ,  Shang-De Chang ,  Han-Chih Lin ,  Tzeng-Huei Shiau ,  I-Sheng Liu ,  Hsien-Wen Liu

发明人： Alex Wang ,  Shang-De Chang ,  Han-Chih Lin ,  Tzeng-Huei Shiau ,  I-Sheng Liu ,  Hsien-Wen Liu

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/42328 ,  H01L29/7883

摘要： A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.